Abstract: Reliability of a gate resistor element during high-temperature operation is enhanced. A semiconductor device includes a drift layer, a base layer, an emitter layer, a gate insulation film, a gate electrode, a gate pad electrode, a first resistance layer, and a first nitride layer. A resistor of the first resistance layer has a negative temperature coefficient. The first resistance layer is made of hydrogen-doped amorphous silicon. The first nitride layer is made of a silicon nitride layer or an aluminum nitride layer.

Abstract: A light emitting device for a display including first, second, and third LED stacks each including a first semiconductor layer, an active layer, and a second semiconductor layer, first, second, and third transparent electrodes in ohmic contact with a lower surface of the first LED stack, an upper surface of the second LED stack, and an upper surface of the third LED stack, respectively, a first electrode pad disposed on the first semiconductor layer of the third LED stack, a lower second electrode pad disposed on the third transparent electrode, and first, second, and third bump pads disposed on the first LED stack and electrically connected to the LED stacks, respectively, and a common bump pad disposed electrically connected to each LED stack, in which an upper surface of the first electrode pad is located at substantially the same elevation as that of the lower second electrode pad.

Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.

Abstract: A light emitting diode display apparatus includes a display substrate having a plurality of subpixel areas; and a light emitting diode disposed on the display substrate to correspond to a corresponding subpixel area of the plurality of subpixel areas, wherein the light emitting diode includes an emission area and a non-emission area adjacent to the emission area, wherein the light emitting diode includes a trench part provided to overlap a boundary between the emission area and the non-emission area, and wherein the trench part is configured such that a side light emitted from the emission area is reflected in a display direction of the light emitting diode display apparatus.

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

Abstract: A solid-state image pickup device includes a semiconductor substrate in which photoelectric conversion units are arranged. An insulator is disposed on the semiconductor substrate. The insulator has holes associated with the respective photoelectric conversion units. Members are arranged in the respective holes. A light-shielding member is disposed on the opposite side of one of the members from the semiconductor substrate, such that only the associated photoelectric conversion unit is shielded from light. In the solid-state image pickup device, the holes are simultaneously formed and the members are simultaneously formed.

Abstract: A semiconductor storage device includes a stacked body including conductive layers stacked in a first direction; columnar bodies of a first group extending in the first direction in the stacked body, wherein memory cell transistors are respectively formed at intersections of the conductive layers and the columnar bodies of the first group; columnar bodies of a second group that are arranged in a second direction, and respectively include an insulating material; and an insulating film extending in the first direction and the second direction in the stacked body, and divides the stacked body to include a first portion adjacent to the columnar bodies of the first group, a second portion adjacent to the columnar bodies of the second group, a third portion between the first portion and the second portion, and a first protruding part protruding from one side surface in the third direction in the third portion.

Abstract: A method of connecting a plurality of electronic components to a flexible circuit board comprises: providing a carrier substrate carrying the electronic components, each of the electronic components having at least one electrical contact coated with electrically conductive adhesive; and applying the carrier substrate to the flexible circuit board such that the electronic components are adhered to the flexible circuit board in electrical contact therewith via the conductive adhesive. The electronic components may comprise LEDs and there may be provided one or more optical layers over the flexible circuit board.

Abstract: Provided are a method for manufacturing a perovskite nanocrystal particle light-emitter where an organic ligand is substituted, a light-emitter manufactured thereby, and a light emitting device using the same. A method for manufacturing an organic-inorganic-hybrid perovskite nanocrystal particle light-emitter where an organic ligand is substituted may comprise the steps of: preparing a solution including an organic-inorganic-hybrid perovskite nanocrystal particle light-emitter, wherein the organic-inorganic-hybrid perovskite nanocrystal particle light-emitter comprises an organic-inorganic-hybrid perovskite nanocrystal structure and a plurality of first organic ligands surrounding the organic-inorganic-hybrid perovskite nanocrystal structure; and adding, to the solution, a second organic ligand which is shorter than the first organic ligands or includes a phenyl group or a fluorine group, thereby substitutes the first organic ligands with the second organic ligand.

Abstract: The present invention teaches a pixel unit including thin film transistors (TFTs) and pixel electrodes corresponding to the TFTs. The pixel electrodes are connected to the source electrodes of the TFTs. Each pixel electrode includes multiple arc-shaped electrode units arranged at intervals along an axial direction around a periphery of a corresponding TFT. The electrode units are electrically connected together. The present invention adopts arc-shaped pixels (similar to concentric circles) so that liquid crystal molecules are closer to being isotropic. Then, by having different vertical alignment (VA) TFT designs in the primary pixel region and secondary pixel region and utilizing the differences in W/L and capacitance, different voltage levels for primary pixel electrode and secondary pixel electrode are achieved. The color shift problem is improved and the viewing angle is enhanced.

Abstract: The present disclosure provides a light-emitting diode, a method for manufacturing the same, a backlight source and a display device. The light-emitting diode includes a support having a bottom wall, a light-emitting chip on the support, and a die bonding structure. A through hole is provided in the bottom wall. At least a portion of the die bonding structure is located in the through hole. The light-emitting chip is attached to the bottom wall through the die bonding structure.

Abstract: An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.

Abstract: Various embodiments provide a process for producing an optoelectronic component. The process includes forming a first electrode and at least one contact section atop a carrier, forming an optically functional layer structure atop the first electrode, forming a second electrode atop the optically functional layer structure, the first electrode or the second electrode being electrically connected to the contact section, applying a protective layer to at least a subregion of the contact section, the protective layer being formed by a material which is repellent to a substance for production of an encapsulation layer, and forming the encapsulation layer atop the second electrode and atop the contact section, the subregion remaining free of the encapsulation layer because of the protective layer.

Abstract: A memory device includes a stack structure, a memory element, a channel element, and a semiconductor layer. The stack structure includes a source layer, an insulating layer and gate electrode layers. The insulating layer is on the source layer. The gate electrode layers are on the insulating layer. The memory element is on electrode sidewall surfaces of the gate electrode layers. Memory cells are defined in the memory element between the channel element and the gate electrode layers. The semiconductor layer is electrically connected between the source layer and the channel element. The semiconductor layer and the source layer have an interface therebetween. The interface is at a location on an inside of an insulating sidewall surface of the insulating layer with a lateral offset relative to the insulating sidewall surface.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.

Abstract: The present invention relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor that has multiple mesas having different widths, configured to promote the buildup and accumulation of hole carriers, thereby facilitating relatively easy subsequent processing, while maximizing conductivity modulation.

Abstract: A device is provided that includes a semiconductor substrate on which a free magnetic element is positioned, which has first and second magnetic domains separated by a domain wall. A first magnet is positioned on the substrate near a first end of the free magnetic element, and has a first polarity and a first value of coercivity. A second magnet is positioned on the substrate near a second end of the free magnetic element, and has a second polarity, antiparallel relative to the first polarity, and a second value of coercivity different from the first value of coercivity.

Abstract: A semiconductor device includes: two first semiconductor regions of a first conductivity type spaced apart from each other; a second semiconductor region of a second conductivity type provided between the two first semiconductor regions; a first insulator region surrounding the two first semiconductor regions and the second semiconductor region; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the second conductivity type, the fourth semiconductor region surrounding the third semiconductor region and the first insulator region and having an impurity concentration of the second conductivity type lower than an impurity concentration of the third semiconductor region; a second insulator region that surrounds the fourth semiconductor region; a conductor layer provided over the second semiconductor region; two first contact plugs; a second contact plug provided on the conductor layer; and a third contact plug provided on the third semiconductor region.

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.