Abstract: A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma containing Cl2, the bond structure comprises: a liner or lower metal layer formed on a predetermined area of the IC substrate; an aluminum-based metal layer formed on the liner layer as the last metal layer for bond purposes; a tungsten based redundancy layer formed on top of the aluminum-based last metal layer; and a passivation layer formed over the IC substrate and on the tungsten based redundancy layer.
Type:
Grant
Filed:
April 30, 2002
Date of Patent:
March 15, 2005
Assignee:
Infineon Technologies AG
Inventors:
Gerald Friese, Werner K. Robl, Hans-Joachim Barth, Axel Brintzinger
Abstract: Briefly described, new types of nanostructures and methods of fabrication thereof are disclosed. A representative nanostructure includes a free-standing, helical semiconductor oxide nanostructure. The free-standing, helical semiconductor oxide nanostructure includes a nanobelt having a substantially rectangular cross-section. The the nanobelt is about 5 nanometers to about 200 nanometers in width and about 3 nanometers to about 50 nanometers in height, and the radius of the helical semiconductor oxide nanostructure is about 200 to 5000 nanometers.
Abstract: A thermally conductive substrate having a structure in which inorganic filler for improving the thermal conductivity and thermosetting resin composition are included. The thermosetting resin composition has a flexibility in the not-hardened state, and becomes rigid after hardening. The thermally conductive substrate has excellent thermal radiation characteristics. The method of manufacturing the thermally conductive substrate includes: piling up (a) the thermally conductive sheets comprising 70 to 95 weight parts of an inorganic filler, and 4.
Type:
Grant
Filed:
December 4, 2002
Date of Patent:
March 8, 2005
Assignee:
Matsushita Electric Industrial Co., Ltd.
Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.
Type:
Grant
Filed:
October 29, 2003
Date of Patent:
March 1, 2005
Assignee:
International Business Machines Corporation
Inventors:
Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi
Abstract: A process for the preparation of a silicon single ingot in accordance with the Czochralski method. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C. to initially produce in the constant diameter portion of the ingot a series of predominant intrinsic point defects including vacancy dominated regions and silicon self interstitial dominated regions, alternating along the axis, and cooling the regions from the temperature of solidification at a rate which allows silicon self-interstitial atoms to diffuse radially to the lateral surface and to diffuse axially to vacancy dominated regions to reduce the concentration intrinsic point defects in each region.
Type:
Grant
Filed:
October 5, 2001
Date of Patent:
February 22, 2005
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Vladimir V. Vornokov, Robert J. Falster, Mohsen Banan
Abstract: Programmable conductor memory cells in a stud configuration are fabricated in an integrated circuit by blanket deposition of layers. The layers include a bottom electrode in contact with a conductive region in a semiconductor substrate, a glass electrolyte layer that forms the body of the cell and a top electrode layer. Under the influence of an applied voltage, conductive paths grow through or along the cell body. The layers are patterned and etched to define separate pillars or cells of these stacked materials. A liner layer of an insulating material is deposited over the cells and acts as a barrier to prevent diffusion of the metal in the cell body into other parts of the integrated circuit. Remaining regions between the cells are filled with an insulating layer. At least some of the insulating layer and some of the liner layer are removed to make contact to the top electrode layer of the cell and to the substrate.
Abstract: The invention provides a semiconductor element having a semiconductor junction composed of silicon-based films, at least one of the silicon-based films containing a microcrystal. The microcrystal is located in at least one interface region of the silicon-based film containing the microcrystal and has no orientation property. Further, the invention provides a semiconductor element having a semiconductor junction composed of silicon-based films, at least one of the silicon-based films containing a microcrystal, and the orientation property of the microcrystal changing in a film thickness direction of the silicon-based film containing the microcrystal. Thereby, a silicon-based film having a shortened tact time, an increased film forming rate, and excellent characteristics, and a semiconductor element including this silicon-based film having excellent adhesion and environmental resistance can be obtained.
Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.
Type:
Grant
Filed:
May 30, 2003
Date of Patent:
February 15, 2005
Assignee:
International Business Machines Corporation
Inventors:
Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi
Abstract: A fire barrier panel of the kind suitable for lining car decks and engine rooms of high speed aluminum ferries is described. The panel (10) includes a relatively thin layer of inorganic insulating material (12) adhered to a lightweight support structure (14). The layer of inorganic insulating material may be an intumescent material made from mineral fibers. The decribed lightweight support structure (14) is a honeycomb panel having a honeycomb core (18) of non-combustible aluminum foil provided with two face skins made of glass reinforced plastics resin material (16). This construction of the honeycomb panel (14) is lightweight and has high stiffness and rigidity suitable for stiffening and supporting the insulating material into a rigid panel. The layer of intumescent material (12) supported on the panel expands when exposed to high temperatures to form a thick fire insulating barrier panel.
Abstract: A wiring board obtained by filling a copper paste in a via hole formed on a ceramic green sheet and firing it to form an insulating layer and a via conductor, the copper paste comprising a copper powder, an organic vehicle and at least one selected from the group consisting of: a ceramic particle having an average particle size of 100 nm or less; and an Fe2O3 particle, wherein the copper paste comprises from 6 to 20 parts by mass of the organic vehicle per 100 parts by mass of the copper powder.
Type:
Grant
Filed:
July 17, 2003
Date of Patent:
February 15, 2005
Assignee:
NGK Spark Plug Co., Ltd.
Inventors:
Hiroshi Sumi, Hidetoshi Mizutani, Manabu Sato
Abstract: A silicon penetration device with increased fracture toughness and method of fabrication thereof are provided. The method comprises strengthening silicon penetration devices by thermally growing a silicon oxide layer on the penetration device and then subsequently stripping the silicon oxide. The method also includes strengthening silicon penetration devices through the sputtering of thin film coatings on the silicon penetration devices.
Type:
Grant
Filed:
June 12, 2003
Date of Patent:
February 8, 2005
Assignee:
Kumetrix, Inc.
Inventors:
Wilson Smart, Kumar Subramanian, Eugene Orloff
Abstract: The purpose of the invention is to provide a forgery/alteration protective material which containing a retroreflecting material and having an improved forgery/alteration protecting effect against the process of the upper part of the material. In order to achieve the above purpose, the forgery/alteration protective material 2 according to the invention where a retroreflecting material 4 for returning the incident light substantially along the path along which the incident light travels is provided and a transparent film 6 is layered on the retroreflecting material 4 is characterized in that a low transmittance layer 8 formed of a material having a lowerer light transmittance than that of the transparent film 6 is provided between the retroreflecting material 4 and the transparent film layer 6, and the light transmittance of the low transmittance layer 8 is 45% or higher to the light in the wavelength range of 420 nm to 700 nm.
Abstract: A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.
Abstract: The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. The process comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, and (iii) a cooling rate of the crystal from solidification to about 750° C., in order to cause the formation of a segment having a first axially symmetric region extending radially inward from the lateral surface of the ingot wherein silicon self-interstitials are the predominant intrinsic point defect, and a second axially symmetric region extending radially inward from the first and toward the central axis of the ingot.
Type:
Grant
Filed:
January 22, 2002
Date of Patent:
January 25, 2005
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Chang Bum Kim, Steven L. Kimbel, Jeffrey L. Libbert, Mohsen Banan
Abstract: An adhesive film for underfill which relaxes the stress formed in the wiring circuit substrate, semiconductor element and electrode parts for connection. The adhesive film is a quickly hardening type, and forms a highly heat resistant sealing resin layer quickly between the wiring circuit substrate and semiconductor element of a semiconductor device.
Abstract: A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide SiOX?2, having a dielectric constant greater than about 3.9 and less than or equal to about 12.
Abstract: The GaN single-crystal substrate 11 in accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020° C. in a mixed gas atmosphere containing at least an NH3 gas. As a consequence, an atomic rearrangement is effected in the surface of the substrate 11 in which a large number of minute defects are formed by polishing, so as to flatten the surface of the substrate 11. Therefore, the surface of an epitaxial layer 12 formed on the substrate 11 can be made flat.
Type:
Grant
Filed:
May 8, 2003
Date of Patent:
January 11, 2005
Assignees:
Sumitomo Electric Industries, Ltd., Institute of Materials Research & Engineering
Abstract: A silica layer is provided which is usable as a low refractive index layer undergoing no change in its refractive index. Further, a silica layer is provided which is highly productive and usable as a medium or high refractive index layer undergoing neither reduction in transmittance nor change in spectral colors. Still further, an antireflection film using these silica layers is provided.
Abstract: A curved laminated automotive glazing panel (10) having a radius of curvature at at least one portion that is less than 500 mm has a glazing panel which is provided with a solar control coating layer (25) positioned at its convex internal surface (11) and in which the coating stack comprises at least two space sputtered silver containing layers initially deposited on a substantially flat sheet of glazing material which is subsequently bent to form a part of the glazing panel (10).
Abstract: The invention concerns transparent fire break glass panels. The inventive glazing comprises at least two glass sheets and an intumescent phosphate-based material layer, layer which is located between said two glass sheets. The intumescent material comprises pyrogenous silica or a mixture of pyrogenous silica and alumina which enables said material to be exempt from creep deformation at temperatures preceding the expansion of the intumescent material in fire resistance tests. The inventive glass panels have proved heat resistance, and are more easily manufactured than similar glass panels in prior art.
Type:
Grant
Filed:
September 11, 2000
Date of Patent:
January 4, 2005
Assignee:
Glaverbel
Inventors:
Pierre Goelff, Guy Mertens, Xavier Dallenogare, Mehdi Ghodsi