Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

Abstract: A display device includes: a first electrode layer; a semiconductor layer including a source region, a drain region, and a channel region, wherein at least a portion of the source region or the drain region overlaps the first electrode layer; a second electrode layer arranged adjacent to the channel region; a third electrode layer overlapping the second electrode layer and at least a portion of the source region or the drain region; and a power line electrically connected to the first electrode layer and the third electrode layer.

Abstract: The disclosure relates to a display panel, a method for fabricating the same, and a display device. The display panel includes: a base substrate, and a thin film transistor structure, an anode layer, a light-emitting layer, a cathode layer, and an encapsulation layer, which are arranged successively on the base substrate, wherein at least one installation hole for installing a hardware structure is arranged in a display area of the display panel, and the installation hole runs through the base substrate and the respective layers on the display panel in the direction perpendicular to the base substrate; and the edge of the installation hole is arranged with an encapsulation layer material, and the encapsulation layer material covers at least the light-emitting layer and the cathode layer adjacent to the edge of the installation hole, in the direction parallel to the base substrate.

Abstract: Light emitting diodes, components, and related methods, with improved performance over existing light emitting diodes. In some embodiments, light emitter devices included herein include a submount, a light emitter, a light affecting material, and a wavelength conversion component. Wavelength conversion components provided herein include a transparent substrate having an upper surface and a lower surface, and a phosphor compound disposed on the upper surface or lower surface, wherein the wavelength conversion component is configured to alter a wavelength of a light emitted from a light source when positioned proximate to the light source.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate comprising a first face, and a second face on an opposite side to the first face. A semiconductor element is provided on the first face of the semiconductor substrate. A polycrystalline or non-crystalline first material layer is provided at least on an outer edge of the first face of the semiconductor substrate. A second material layer is provided on the second face of the semiconductor substrate. The second material layer transmits laser light.

Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.

Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

Abstract: An infrared detector includes a pixel separation wall. The infrared detector includes a semiconductor crystal substrate; a first contact layer formed on the semiconductor crystal substrate, a pixel separation wall formed on the first contact layer and configured to separate pixels; a buffer layer formed on the first contact layer and on a side surface of the pixel separation wall in a region surrounded by the pixel separation wall, an infrared-absorbing layer formed on the buffer layer, a second contact layer formed on the infrared-absorbing layer, an upper electrode formed on the second contact layer, and a lower electrode formed on the first contact layer. The buffer layer and the first contact layer are formed of a compound semiconductor of a first conductivity type. The pixel separation wall and the second contact layer are formed of a compound semiconductor of a second conductivity type.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 5×10?8 ohm meters and controlled by at least one of the metals that form the first conductive alloy material.

Abstract: A thin film transistor includes a substrate, a semiconductor layer, a first gate insulating film, a second gate insulating film, and a gate electrode. The semiconductor layer is provided in a selective region of the substrate. The first gate insulating film is provided in the selective region of the substrate and covers a surface of the semiconductor layer. The second gate insulating film extends across opposite sides of the first gate insulating film along a channel width direction and covers the first gate insulating film that covers the semiconductor layer. The gate electrode faces the semiconductor layer across the second gate insulating film.

Abstract: Four conjugated copolymers with a donor/acceptor architecture including 4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b?]dithiophene as the donor structural unit and benzo[2,1,3]thiodiazole fragments with varying degrees of fluorination have been synthesized and characterized. It has been shown that the HOMO levels were decreased after the fluorine substitution. The field-effect charge carrier mobility was similar for all polymers with less than an order of magnitude difference between different acceptor units.

Abstract: An organic light-emitting display apparatus including: a substrate; a plurality of first electrodes spaced apart from each other on the substrate; a plurality of organic functional layers respectively covering an upper surface and side surfaces of the plurality of first electrodes, each of the plurality of organic functional layers including an emission layer; a first bank disposed between the plurality of organic functional layers and not directly contacting the plurality of first electrodes; and a second electrode disposed on the plurality of organic functional layers.

Abstract: An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.

Abstract: Light emitting diodes, components, and related methods, with improved performance over existing light emitting diodes. In some embodiments, light emitter devices included herein include a submount, a light emitter, a light affecting material, and a wavelength conversion component. Wavelength conversion components provided herein include a transparent substrate having an upper surface and a lower surface, and a phosphor compound disposed on the upper surface or lower surface, wherein the wavelength conversion component is configured to alter a wavelength of a light emitted from a light source when positioned proximate to the light source.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate, a reflection region layered structure and a reflection electrode. The base substrate includes a pixel region, the pixel region includes a reflection region. The reflection region layered structure is in the reflection region, and includes a particle layer, the particle layer is configured to provide a granular rough surface on a side of the reflection region layered structure facing away from the base substrate. The reflection electrode is on the particle layer.

Abstract: An optical package structure includes a substrate, an optical element, a spacer and an encapsulant. The substrate has a top surface. The optical element is disposed adjacent to the top surface of the substrate and has a first height H1. The spacer surrounds the optical element and has a top surface. A distance between the top surface of the substrate and the top surface of the spacer is defined as a second height H2. The encapsulant is disposed between the optical element and the spacer, and has a third height H3 at a position adjacent to the optical element. The encapsulant covers at least a portion of the optical element. The optical element is exposed from the encapsulant, and H2>H1?H3.

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above at least an active region, wherein the gate structure has an axial length in a direction corresponding to a gate width direction of the transistor device. In this example, a first portion of the axial length of the gate structure has a first upper surface and a second portion of the axial length of the gate structure has a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface. The device also includes a gate contact structure that contacts the first upper surface of the gate structure.