Abstract: Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.

Abstract: Disclosed circuitry includes input-output pads, receive flip-flops, and transmit flip-flops coupled to the input-output pads. Data path control circuitry is coupled to data path control flip-flops, the receive flip-flops and the transmit flip-flops. The data path control circuitry is configured to selectably couple the receive flip-flops and the transmit flip-flops to the input-output pads in response to states of the data path control flip-flops. Clock control circuitry is coupled to clock control flip-flops, the receive flip-flops and the transmit flip-flops. The clock control circuitry is configured to selectably apply one of multiple clock signals to the receive flip-flops and the transmit flip-flops in response to states of the clock control flip-flops. A first scan chain is coupled to the clock control flip-flops and the data path control flip-flops. A second scan chain is coupled to the receive flip-flops and the transmit flip-flops.

Abstract: Communication endpoints and related methods for forward error correction (FEC) are disclosed. A communication endpoint includes control circuitry including a packetizer configured to segment near-end data into groups of near-end data packets, and a forward error correction (FEC) packet generator configured to generate at least two near-end FEC packets for each group of near-end data packets. A method includes generating the FEC packets, and transmitting the data packets and the FEC packets to a far-end communication endpoint. A communication endpoint includes control circuitry including a forward error correction repairer configured to use far-end FEC packets to repair groups of far-end data packets. A method includes receiving a group of far-end data packets and corresponding far-end FEC packets, and repairing far-end data packets with the corresponding far-end FEC packets.

Abstract: A test device includes: a test control unit suitable for detecting a deterioration-expected unit circuit among a plurality of unit circuits included in a test-subject device according to operation histories of the plural unit circuits, and detecting a deterioration degree according to a test output value of the deterioration-expected unit circuit; and an interface unit suitable for routing control operation results and test results between the test control unit and the test-subject device during a test operation.

Abstract: Provided is a storage device, a liquid container and a host device that appropriately control whether or not writing is to be performed with an efficient data configuration. The storage device 100 includes a control unit 110 that performs processing for communication with a host device 400, a storage unit 120, and a storage control unit 130 that performs access control on the storage unit 120. The control unit 110 receives a write data packet from the host device 400, and if a data pattern of write data included in the write data packet and additional data is judged as not matching a specific pattern, makes update instruction of address information and write instruction regarding write data to the storage control unit 130. If judged as matching, the control unit 110 does not make a write instruction regarding the write data, while making an update instruction of the address information.

Abstract: Technology is described for generating a valid token control signal from control signals from a row driver. In one example, a matrix type integrated circuit includes a row driver module and a 2D array of cell elements. The row driver module includes a voting logic module and at least two row drivers configured to generate control signals on at least two communal lines for cell elements of a row of the 2D array. Each row driver is configured to generate control signals on at least three control lines where at least two control lines are the communal lines and coupled to a corresponding communal line of another row driver. The voting logic module is coupled to the at least three control lines of one of the row drivers and configured to generate an output based on the control signals on the at least three control lines.

Abstract: A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.

Abstract: A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

Abstract: A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K?N, L>1, P?M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.

Abstract: Disclosed herein is a broadcast signal transmitter. A broadcast signal transmitter according to an embodiment of the present invention includes a first BICM unit configured to FEC-encode the data of a core layer, a second BICM unit configured to FEC-encode the enhanced layer data, an LDM injection unit configured to combine the core layer data and the enhanced layer data and to output Layered Division Multiplexing (LDM) data, a time interleaver configured to time-interleave the LDM data, a framing unit configured to generate a signal frame including a preamble for carrying signaling information and the LDM data, and a waveform generation unit configured to generate a broadcast signal by performing OFDM modulation on the signal frame.

Abstract: An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.

Abstract: A low density parity check (LDPC) decoding method and a decoding apparatus are provided. The method includes following steps. Based on M edges of a Tanner graph related to a parity check matrix, each of the edges is associated with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifies. When executing one of the threads, data in a shared memory is accessed according to the edge identifier of the one of the threads, so as to update a plurality of passing massages respectively corresponding to the edges in the shared memory. Thereby, high computation parallelism and fully-coalesced data accesses can be achieved.

Abstract: A method for fast decoding, the method may include (a) performing a hard read of a group of flash memory cells to provide hard read data; wherein the group of flash memory cells store a codeword that comprises component codes of multiple dimensions; (b) hard decoding the hard read data to provide a hard decoding result; wherein the hard decoding result comprises first suggested values of component codes of at least one dimension of the multiple dimensions; (c) performing at least one additional read attempt of the group of flash memory cells to provide additional data; (d) performing a partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result; and (e) wherein the soft decoding result comprises second suggested values of component codes of one or more dimensions of the multiple dimensions.

Abstract: A defect scan method is carried out to detect a defective portion in a storage medium of a storage device, the storage medium including multiple storage regions including a first storage region and a second storage region. The defect scan method includes scanning a part of the storage regions of the storage medium to detect a defective portion therein, before the storage device is connected to a host, a scanned storage region including the first storage region and a non-scanned storage region including the second storage region, mapping logical addresses to physical addresses of a non-defective portion of the first storage region, scanning the second storage region to detect a defective portion therein, after the storage device is connected to the host, and mapping logical addresses to physical addresses of a non-defective portion of the second storage region.

Abstract: The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.

Abstract: A method for transmitting an input stream of data across a serial link including a serial channel. The method includes segmenting the stream of data into blocks of bits to form input blocks, and for each input block, calculating a measure of burst error probability, forming an output block and a modification signaling bit from the input block, transmitting the output block, and transmitting the modification signaling bit. The forming of the output block and the modification signaling bit from the input block includes, when the measure of burst error probability exceeds a set threshold: modifying the input block to form the output block, and asserting the modification signaling bit.

Abstract: Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks.