Abstract: One embodiment provides a method for resolving a forward error correction (FEC) protocol. The method includes requesting, by a network node element during an auto-negotiation period between the node element and a link partner, to resolve at least one FEC mode during a link training period; wherein the auto-negotiation period and the link training period are defined by an Ethernet communications protocol and the auto-negotiation period occurs before the link training period; determining, by the network node element, at least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner; and determining, by the network node element during the link training period, whether to enable at least one FEC mode for use by the network node element based on, at least in part, the at least one channel quality parameter.

Abstract: Embodiments of the present invention provide a system that identifies an even delimiter in a forward error correction (FEC)-coded Ethernet frame. The system receives an FEC-coded Ethernet frame that includes the even delimiter, which is a predetermined sequence that separates a conventional Ethernet frame and FEC parity bits in the FEC-coded Ethernet frame. Next, the system scans a bit stream of the FEC-coded Ethernet frame. Then, the system determines a first Hamming distance between a first consecutive set of frame bits in the bit stream and the even delimiter. The system also determines a second Hamming distance between a second consecutive set of frame bits in the bit stream and the even delimiter. Both the first and second Hamming distances are shorter than a predefined value. The system subsequently selects one of the first and second sets of frame bits having the shorter Hamming distance as the even delimiter.

Abstract: A signal processing system includes a module under test, an oscillation signal generator, a translational filter, and a testing module. The module under test has a signal input end. The oscillation signal generator generates an oscillation signal. The translational filter includes a mixer controlled by the oscillation signals. The mixer has a high-frequency side and a low-frequency side. The high-frequency side is coupled to the signal input end of the module under test. The testing module is coupled to the low-frequency side of the mixer. When the signal processing system is in a testing mode, the testing module provides a testing signal to the low-frequency side, so as to generate a high-frequency testing signal at the high-frequency side of the mixer.

Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

Abstract: A flash device is provided. A flash memory includes a plurality of pages. A controller coupled to the flash memory includes an operating unit, an error correction code (ECC) decoder and a processing unit. The operating unit receives a plurality of bytes of the page which are from the flash memory and corresponding to a read command, and obtains an operating result according to a logic level of each bit of each of the bytes. The ECC decoder decodes the bytes of the page according to an ECC code. The processing unit determines whether the page is valid data according to the decoded bytes, and determines whether the page is an empty page according to the operating result when the page is not the valid data.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Abstract: A method for non-uniform multiple dimensional decoding, the method may include receiving or generating a multiple dimensional encoded data unit; and decoding by a processor the multiple dimensional encoded data unit to provide a decoded data unit; wherein the multiple dimensional encoded data unit comprises multiple component codes associated with multiple dimensions; wherein the multiple dimensions comprise a plurality of non-uniform dimensions; wherein at least two component codes of each non-uniform dimension differ from each other by encoding rate; wherein the decoding is responsive to encoding rates of component codes of the plurality of non-uniform dimensions.

Abstract: An encoder for error correction code encoding input data words (D) into codewords (Z1, Z2) includes an encoder input for receiving input data words each including a first number Kldpc of information symbols, an encoding unit for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword includes a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number N ldpc - Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, and an encoder output for outputting the codewords (Z1, Z2).

Abstract: A method includes initiating a first decode operation of data at an error correction code (ECC) hard bit decoder in a data storage device that includes a controller and a memory. The method further includes, in response to the first decode operation indicating that the data is uncorrectable by the first decode operation, identifying one or more bits of the data that correspond to a disturb condition test pattern, changing a value of the one or more identified bits of the data to generate modified data, and initiating a second decode operation at the ECC hard bit decoder using the modified data.

Abstract: An apparatus has a shared fuse array and a plurality of x86-compatible microprocessors disposed on a die. The shared fuse array has a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes accessible by a plurality of x86-compatible microprocessors and another plurality of semiconductor fuses programmed with uncompressed system hardware configuration data that is employed to initialize control circuit elements within the plurality of x86-compatible microprocessors. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessors is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of microprocessors.

Abstract: Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.

Abstract: A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. In one case a data processing system is disclosed that includes a decoder circuit operable to apply a low density parity check algorithm to a decoder input to yield an interim decoded output, where the decoder input is a codeword formed of two bit symbols, and where the decoder input is encoded to yield a last layer including at least two different entry values. In addition, the data processing system includes an inverse mapping circuit operable to remap the interim decoded output to yield an overall decoded output.

Abstract: According to one embodiment, an encoding apparatus includes an encoding unit. The encoding unit encodes a data bit sequence to generate a codeword corresponding to a parity check matrix. The parity check matrix is based on a protograph. In the protograph, each of n check nodes of a first type is connected to n variable nodes of a first type by a total of at least one edge of a first type, and to n variable nodes of a second type by a total of at least two edges of a second type. In the protograph, each of n check nodes of a second type is connected to the n variable nodes of the second type by a total of r edges of a third type, and to n variable nodes of a third type by a total of g edges of a fourth type.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.

Abstract: A computer implemented method of controlling the decoding of codewords received by a linear block code pipelined decoder from an input buffer, the pipelined decoder comprising at least two decoding stages. The method comprises iteratively: loading the decoding stages of the pipelined decoder, executing a decoding step, determining the number of residual errors in the codewords and outputting error free codewords. The method allows the different decoding stages to be loaded with any codeword coming from the buffer or from any decoding stage of the decoder. Accordingly, the occupation rate of the pipeline is improved.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.

Abstract: Systems and methods are provided for decoding data. A decoder retrieves data related to a symbol and identifies a plurality of candidate values for the symbol. The decoder determines a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances, and the decoder determines whether to update a value of the symbol based at least in part on the plurality of distances.