Abstract: An integrated circuit device includes an output buffer circuit that provides a first output having a first code rate. The first output is provided in response to a first indication of a change in a parameter that affects an error rate of the first output. The first output includes redundant information. The output buffer circuit provides a second output having a second code rate. The second output is provided in response to a second indication of the second output having an error rate that is different than the error rate of the first output. The second code rate of the second output is different than the first code rate.

Abstract: A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an FEC encoded word of the set of FEC encoded words. The method continues with the processing module affiliating an address of allocated address space of a dispersed storage memory with the word name and storing the integrity information, the word name, and the address. The method continues with the processing module creating a write command to store the FEC encoded word at the address in the dispersed storage memory.

Abstract: A signal protector utilizes a variable latency station to provide error correction.

Abstract: A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission.

Abstract: An encoder includes: an input configured to receive a plurality of data bits; a processor configured to encode the data bits utilizing a Hamming encoding operation to generate a plurality of coded bits; and an output configured to output the plurality of coded bits, wherein the processor is configured to reduce a maximum run length of the plurality of coded bits in comparison to coded bits corresponding to standard Hamming code.

Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values.

Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

Abstract: An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Abstract: A method for transmitting and receiving ARQ feedback information in a wireless communication system is disclosed. A method for allowing a mobile station to transmit an ARQ feedback in a broadband wireless access system includes receiving an ARQ block and an ARQ feedback polling from the base station, wherein the ARQ feedback polling requests the mobile station to transmit ARQ feedback information indicating whether the ARQ block is successfully received, receiving a first uplink resource for transmitting the ARQ feedback from the base station, and determining whether the received ARQ block is successfully received. The first uplink resource has a minimum size capable of being allocated to the ARQ feedback information.

Abstract: An operating method of an ECC decoder includes receiving first chunk data and second chunk data from a nonvolatile memory device, the second chunk data subsequent to the first chunk data, performing error correction on the first chunk data, determining if the first chunk data includes an uncorrectable error bit and determining not to perform error correction on the second chunk data in response to the first chunk data including the uncorrectable error bit.

Abstract: A method includes, responsive to a power-up event at a data storage device that includes a memory, reading a flag stored at the data storage device and determining that the flag has a first value indicating that a reflow operation has not previously been detected at the memory. The method also includes, in response to determining that the flag has the first value, performing reflow detection at the memory. The method further includes, in response to the reflow detection indicating that the reflow operation has occurred, setting the flag to a second value.

Abstract: In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.

Abstract: A coding device, such as a memory device or communication system, comprising encoder circuitry configured to encode data into inner codewords and multiple-strength Reed-Solomon outer codewords, the Reed-Solomon outer codewords including weak strength, mid-strength, and strong strength. The strength of the codewords can be varied by changing at least one of the code length N, data length K, parity length R, symbol size S and code rate K/N.

Abstract: Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.

Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

Abstract: IC device comprising a plurality of functional components arranged into self-test cells. The IC device is configurable into a first self-test configuration comprising a first set of self-test partitions. Each self-test partition within the first set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the first set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the first self-test configuration. The IC device is configurable into a second self-test configuration comprising a second set of self-test partitions. Each self-test partition within the second set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the second set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the second self-test configuration.

Abstract: Disclosed in a novel scheme to jointly reduce and trade-off Peak-to-Average Power Ratio (PAPR) and a Block Error Rate (BLER) using random network coding. To do this, the different representations of the input information block are generated using a special form of network coding matrices. Further, the encoded block puncturing is utilized to improve in the PAPR against a degradation in the BLER.

Abstract: An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is determined. It is ensured that a duplicate of data content associated with the first physical memory line is associated with a second physical memory line. The physical memory address is remapped to use the second physical memory line for data content.

Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.