Abstract: Some embodiments of the invention are directed to systems and methods for an optimized and efficient encoding scheme that can accommodate higher block lengths of data. Some embodiments generally relate to: (1) coding structures for a new class of LDPC matrices based on algebraic relations, and (2) encoding method that achieves the R=1?k/n exact bound on code rate. In addition, in some embodiments, the coding structures efficiently create matrices with excellent error-correcting properties and are devoid of short cycles (leading to robust performance). The implementations of the coding structures are scalable over a range of code rates and block lengths.

Abstract: A circuit includes a plurality of scan chains each including a plurality of scan blocks. Each scan block includes a storage element and a switching device having an output directly coupled to an input of the storage element. The switching device has a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed and a second input configured to receive one of a function logic output signal or a scan input signal. The switching device is configured to selectively couple the first input or the second input to the input of the storage element.

Abstract: A method begins by a DS processing module generating a plurality of encoded slices from a data segment using an error encoding function. The method continues with the DS processing module identifying a plurality of DS storage units for storing the plurality of encoded slices. The method continues with the DS processing module selecting an encoded slice of the plurality of encoded slices for sub-slicing using a sub-slicing encoding function to produce a selected encoded slice. The method continues with the DS processing module outputting the plurality of encoded slices to the plurality of DS storage units. The method continues with the DS processing module outputting a command to a DS storage unit of the plurality of DS storage units corresponding to the selected encoded slice, wherein the command includes an instruction to sub-slice the selected encoded slice.

Abstract: A signal protector utilizes a variable latency station to provide error correction.

Abstract: In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

Abstract: The various implementations described herein include systems, methods and/or devices for enhancing the performance of error control decoding. The method includes receiving at an LDPC decoder data from a storage medium corresponding to N variable nodes. The method further includes: updating a subset of the N variable nodes; updating all check nodes logically coupled to the updated subset of the N variable nodes; and generating check node output data for each updated check node including at least an updated syndrome check. Finally, the method includes: stopping decoding of the read data in accordance with a determination that the syndrome checks for all the M check nodes are valid syndrome checks or initiating performance of the set of operations with respect to a next subset of the N variable nodes in accordance with a determination that the syndrome checks for all the M check nodes include one invalid syndrome check.

Abstract: A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.

Abstract: In a DTV transmitter the bits of shortened BCH codewords that exhibit undesirably low densities of ONEs are ONEs' complemented before being further coded, and used to modulate carrier waves. In a DTV receiver the further coding is decoded after demodulation. The results of such decoding are processed to recover successive shortened BCH codewords, some of which are in TRUE form and others of which have had their bits ONEs' complemented. Each shortened BCH codeword is extended to full length with ZEROs, and decoding is attempted. Successful decoding confirms that the shortened BCH codeword was received in TRUE form. If decoding is unsuccessful, the bits of the shortened BCH codeword as received are ONEs' complemented, extended to full length with ZEROs, and decoding is attempted. Successful decoding confirms that the shortened BCH codeword was received in ONEs' complemented form and has subsequently been converted to TRUE form.

Abstract: Methods and devices provide a feedback message having unequal error protection. The feedback message may include channel quality indicators. The channel quality indicators may have different levels of error protection based on a transmission property.

Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.

Abstract: A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Abstract: A memory device and method, such as a flash memory device and method, includes a memory having a plurality of nonvolatile memory cells for storing stored values of user data. The memory device and method includes a memory controller for controlling the memory. The memory controller includes an encoder for encoding user write data for storage of code values as the stored values in the memory. The encoder includes an inserter for insertion of an indicator as part of the stored values for use in determining when the stored values are or are not in an erased state. The memory controller includes a decoder for reading the stored values from the memory to form user read data values when the stored values are not in the erased state.

Abstract: It is a purpose of the invention to provide a fault detection system, etc., having improved fault coverage with a reduced number of test patterns to be input to a logic circuit. The fault detection system detects a fault in a logic circuit based on multiple output logic values of the logic circuit after a test input pattern is input. The output logic values are input to the logic circuit as an updated test input pattern. The system comprises: a first acquisition unit which acquires a part of or all of the output logic values; a comparison unit which compares the logic values acquired by the first acquisition unit with those predicted for when there are no faults, or for when there is a specific fault; and a fault judgment unit which judges whether or not there is a fault based on the comparison result obtained by the comparison unit.

Abstract: According to one embodiment, a transmitter includes a signal dividing unit, a syndrome sending unit, a syndrome receiving unit and a decoding unit. The signal dividing unit divides an original signal into a first signal and a second signal based on a common dividing policy. The syndrome sending unit sends the first syndrome message calculated based on the first signal through a clear channel. The syndrome receiving unit receives a second syndrome message through the clear channel. The decoding unit decodes the second signal by using the second syndrome message to restore a fourth signal, the fourth signal being corresponding to the second signal received by a receiver through a noisy channel.

Abstract: Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair.

Abstract: A method for execution by a DS storage unit begins with the DS storage unit receiving an encoded slice of a plurality of encoded slices, wherein the plurality of encoded slices was generated from a data segment using an error encoding function. The method continues with the DS storage unit determining whether the encoded slice is to be sub-sliced using a sub-slicing encoding function. The method continues with the DS storage unit generating a plurality of encoded sub-slices from the encoded slices using the encoded sub-slicing encoding function when the encoded slice is to be sub-sliced. The method continues with the DS storage unit outputting the plurality of encoded sub-slices to a plurality of DS storage units.

Abstract: A data storage device is disclosed comprising a non-volatile memory (NVM), wherein data is read from the NVM to generate a two dimension matrix of signal samples, including a first dimension and a second dimension. The matrix of signal samples is first equalized to reduce intersymbol interference (ISI) in the first dimension to generate second dimension signal samples, and second equalized to reduce ISI in the second dimension to generate first dimension signal samples. A first data sequence is detected in response to the first dimension signal samples, and a second data sequence is detected in response to the second dimension signal samples.

Abstract: A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining.

Abstract: The present technique relates to data processing devices and data processing methods that can increase tolerance for data errors. In a case where a predetermined LDPC code having a code length of 16200 bits and a code rate of 8/15 is mapped on 256 signal points, and the (#i+1)th bit counted from the uppermost bit among 8×1 sign bits and the (#i+1)th bit counted from the uppermost bit among 8×1 symbol bits of one symbol are expressed as a bit b#i and a bit y#i, respectively, a demultiplexer performs shuffling to assign a bit b0 to a bit y2, a bit b1 to a bit y6, a bit b2 to a bit y1, a bit b3 to a bit y0, a bit y4 to a bit y7, a bit b5 to a bit y5, a bit b6 to a bit y3, and a bit b7 to a bit y4. The present technique can be applied to transmission systems that transmit LDPC codes, for example.