Abstract: Provided is a micro-electro-mechanical system and an electro-acoustic conversion device having the micro-electro-mechanical system. The micro-electro-mechanical system includes: first and second membranes arranged opposite to each other; support members arranged between the first and second membranes; and an opening provided on the first and/or second membranes. Each support member includes support walls, and opposite ends of each of the support walls are connected to the first and second membranes. The first and second membranes, and two adjacent support walls in one support member are enclosed to form a first chamber. The opening is configured to link the first chamber with the outside. By arranging a supporting member composed of support walls and providing an opening on the first and/or second membranes, the compliance of the first or second membrane is increased, and the inter-plate capacitance therebetween is reduced.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an e-fuse with metal fill structures and methods of manufacture. The structure includes: an insulator material; an e-fuse structure on the insulator material; a plurality of heaters on the insulator material and positioned on sides of the e-fuse structure; and conductive fill material within a space between the e-fuse structure and the plurality of heaters.

Abstract: The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.

Abstract: A semiconductor device includes a semiconductor substrate, a doped region formed in the semiconductor substrate, a source/drain formed in the doped region, a conductive pad formed on the source/drain, a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the conductive pad, a gate formed on the gate dielectric layer, an insulation layer formed over the gate, the gate dielectric layer, and the conductive pad, and a contact formed in the insulation layer in electric contact with the conductive pad.

Abstract: A semiconductor device, comprises a source structure comprising an active source portion, an inactive source portion spaced apart from the active source portion in a vertical direction, and a first dielectric structure interposed between the active source portion and the inactive source portion. A drain structure is spaced apart from the source structure in a first direction. A channel layer is disposed on outer surfaces of the source and the drain structures. A memory layer is disposed on an outer surface of the channel layer so as to wrap around the channel layer. At least one gate layer is in electrical communication with the active source portion.

Abstract: An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

Abstract: A light-emitting substrate includes a base substrate, an auxiliary electrode line, at least one light-emitting device, and at least one light-detecting device. The auxiliary electrode line is disposed on the base substrate. The at least one light-emitting device is disposed above the base substrate, and a light-emitting device includes a first electrode, a light-emitting functional layer and a second electrode that are sequentially stacked in a direction moving away from the base substrate. The at least one light-detecting device is disposed above the base substrate, and a light-detecting device includes a third electrode and a fourth electrode. The auxiliary electrode line is coupled to the fourth electrode and the second electrode.

Abstract: A display device includes a display panel including a plurality of sub-pixel areas for respectively outputting light for displaying an image and a light travel-direction changing layer disposed on the display panel for diversifying and spreading travel directions of light emitted from each of the plurality of sub-pixel areas. The light travel-direction changing layer includes a plurality of refractive patterns respectively corresponding to the plurality of sub-pixel areas and arranged in a matrix form, and a light-scattering layer disposed around each of the plurality of refractive patterns and having a refractive index different from a refractive index of each of the plurality of refractive patterns. Due to the light travel-direction changing layer, light from each sub-pixel area is incident into each refractive pattern, is refracted at a boundary between each refractive pattern and the light-scattering layer, and is scattered in the light-scattering layer.

Abstract: A fabricating method of a high voltage transistor includes providing a high voltage transistor. The high voltage transistor includes a substrate. A gate structure is disposed on the substrate. A source drift region and a drain drift region are respectively disposed at two sides of the gate structure and embedded within the substrate. A source is disposed in the source drift region. A drain is disposed within the drain drift region. The steps of fabricating the drain drift region include defining a drain drift region predetermined region on the substrate by using a photo mask. The photo mask includes a first comb-liked pattern. The first comb-liked pattern includes a first rectangle and numerous first tooth structures. Then, an ion implantation process is performed to implant dopants into the drain drift region predetermined region. Then, dopants in the drain drift region predetermined region are diffused to form the drain drift region.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, first gate structures, second gate structures, first source-drain doped layers, second source-drain doped layers, and a first dielectric layer. A top surface of the first dielectric layer disposed over the first region is lower than a top surface of the first dielectric layer disposed over the second region. The semiconductor structure also includes a first barrier layer disposed over the first dielectric layer disposed over the first region. The first barrier layer and the first dielectric layer disposed over the first region include a first opening exposing the first source-drain doped layer, and the first dielectric layer disposed over the second region includes a second opening exposing the second source-drain doped layer.

Abstract: A static random-access memory (SRAM) device including a three-dimensional structured (3DS) field-effect transistor (FET) having a minimized planar area and a simple wiring connection structure includes a semiconductor substrate, a first fin active region extending on the semiconductor substrate in a first direction, a second fin active region extending on the semiconductor substrate in the first direction and apart from the first fin active region in a second direction perpendicular to the first direction, and four gates extending in the second direction and intersecting part of the first fin active region or the second fin active region. Each of the first fin active region and the second fin active region includes a first region in which only a lower layer is arranged and a second region in which an upper layer is arranged on the lower layer.

Abstract: Disclosed are a display substrate and a display apparatus. The display substrate, includes base, and an organic electroluminescent display layer, a touch layer, a polarizer and a cover plate sequentially stacked on the base. The organic electroluminescent display layer and the touch layer are bonded with a first bonding layer, and the polarizer and the cover plate are bonded with a second bonding layer. The display substrate includes a camera installation area and a display area surrounding the camera installation area. A camera is installed on a side of the base away from the organic electroluminescent display layer and located in the camera installation area, a light-emitting layer is not provided in an area of the organic electroluminescent display layer corresponding to the camera installation area, and a first opening is provided in an area of the polarizer corresponding to the camera installation area.

Abstract: The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the second sacrificial layer in the transistor region to form a first gap; and forming a gate layer and a channel layer wrapping the gate layer in the first gap.

Abstract: A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.

Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.

Abstract: A method for fabricating a semiconductor device includes forming a bit line contact hole in a substrate; forming a first spacer on a sidewall of the bit line contact hole; forming a sacrificial spacer over the first spacer; forming a first conductive material that fills the bit line contact hole over the sacrificial spacer; forming a second conductive material over the first conductive material; forming a bit line by etching the second conductive material; and forming a bit line contact plug and a gap between the bit line contact plug and the first spacer by partially etching the first conductive material and the sacrificial spacer to be aligned with the bit line.

Abstract: A display device includes a display panel, a circuit board, a first conductive film, first and second lower films, and first and second adhesive layers. The display panel includes a display area and a pad area which includes a first pad part. The circuit board is attached on the display panel and includes a lead part overlapping the first pad part. The first conductive film is between the display panel and the circuit board and electrically connects the first pad part and the lead part to each other. The first and second lower films are attached to the display panel to respectively correspond to the display area and the pad area. A thickness of the second adhesive layer between the display panel and the second lower film is less than a thickness of the first adhesive layer between the display panel and the first lower film.

Abstract: A device includes a buried oxide layer disposed on a substrate, a first region disposed on the buried oxide layer and a first ring region disposed in the first region. The first ring region includes a portion of a guardring. The device further includes a first terminal region disposed in the first ring region, a second ring region disposed in the first region and a second terminal region disposed in the second ring region. The first terminal region is connected to an anode and the second terminal region is connected to a cathode. The first region has a graded doping concentration. The first region, the second ring region and the second terminal region have a first conductivity type, and the first ring region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: A display device includes a substrate that includes a display area and a pad area, and a plurality of data pads that are provided on the pad area of the substrate and arranged along a first direction and a second direction, where the plurality of data pads includes a first data pad, a second data pad that is disposed adjacent to the first data pad along the first direction, a third data pad that is disposed adjacent to the first data pad along the second direction, and a fourth data pad that is disposed adjacent to the second data pad along the second direction, and the first data pad and the second connection wire are respectively disposed in different layers.