Abstract: The present disclosure is related to a light emitting diode. The light emitting diode may include a pixel unit which may include a first sub-pixel. The first sub-pixel may include a dummy electrode layer and a first electrode layer on the dummy electrode layer. The dummy electrode layer may include a first reflective layer. The first electrode layer may include a second reflective layer and a second transparent conductive layer on the second reflective layer.

Abstract: A display panel is provided, including a substrate and an organic light-emitting component disposed on the substrate. The display panel further includes a planarization layer and an insulation layer disposed on the planarization layer. An anode of the organic light-emitting component is disposed on the planarization layer. The insulation layer is disposed on the planarization layer and configured to cover the planarization layer, and the anode of the organic light-emitting component is exposed through the insulation layer.

Abstract: The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be formed over a conductive substrate by converting at least a portion of the conductive substrate to CEM.

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.

Abstract: An electronic device includes a semiconductor die, an enclosure, leads extending outwardly from the enclosure and electrically connected to the semiconductor die, and wherein the leads have a reduced cross-sectional area along a longitudinal length of the lead. The electronic device is designed to reduce the occurrence of crack formation between the leads and a printed circuit board.

Abstract: According to one or more embodiments of the present invention, a crossbar array includes a cross-point synaptic device at each cross-point. The cross-point synaptic device includes a transistor that includes a first ion reservoir formed on a source and on a drain of the transistor. The transistor further includes an ion conductivity electrolyte layer formed on the first ion reservoir. The transistor further includes a second ion reservoir formed on the ion conductivity electrolyte layer. The transistor further includes a gate formed on the second ion reservoir.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed over the substrate, a gate insulation layer disposed on the resistance change layer, a gate electrode layer disposed on the gate insulation layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed respectively over the substrate and disposed to contact a different portion of the resistance change layer.

Abstract: The present disclosure relates to an electrical fuse (e-fuse) device and a method for forming the electrical fuse device. The vertical e-fuse device includes a fuse link disposed over a semiconductor base. A material of the fuse link and a material of the semiconductor base are the same. The vertical e-fuse device also includes a first bottom anode/cathode region and a second bottom anode/cathode region disposed over the semiconductor base. A bottom portion of the fuse link is sandwiched between the first bottom anode/cathode region and the second anode/cathode region. The vertical e-fuse device further includes a top anode/cathode region disposed over the fuse link.

Abstract: A semiconductor structure, a method for producing a semiconductor structure and a light emitting device are disclosed. In an embodiment a semiconductor structure includes a plurality of discrete encapsulated semiconductor nanoparticles and a plurality of discrete semiconductor free nanoparticles, wherein the discrete encapsulated semiconductor nanoparticles and the discrete semiconductor free nanoparticles form an agglomerate.

Abstract: A current switching semiconductor device to be used in a power conversion device achieves both a low conduction loss and a low switching loss. The semiconductor device includes the IGBT in which only Gc gates are provided and an impurity concentration of the p type collector layer is high, and the IGBT in which the Gs gates and the Gc gates are provided and an impurity concentration of the p type collector layer is low. When the semiconductor device is turned off, the semiconductor device transitions from a state in which a voltage lower than a threshold voltage is applied to both the Gs gates and the Gc gates to a state in which a voltage equal to or higher than the threshold voltage is applied to the Gc gates prior to the Gs gates.

Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Abstract: Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.

Abstract: A method is for depositing silicon nitride by plasma-enhanced chemical vapour deposition (PECVD). The method includes providing a PECVD apparatus including a chamber and a substrate support disposed within the chamber, positioning a substrate on the substrate support, introducing a nitrogen gas (N2) precursor into the chamber, applying a high frequency (HF) RF power and a low frequency (LF) RF power to sustain a plasma in the chamber, introducing a silane precursor into the chamber while the HF and LF RF powers are being applied so that the silane precursor forms part of the plasma being sustained, and subsequently removing the LF RF power or reducing the LF RF power by at least 90% while continuing to sustain the plasma so that silicon nitride is deposited onto the substrate by PECVD.

Abstract: The present disclosure discloses an array substrate, a manufacturing method thereof, a display substrate, and a display device, belonging to the technical field of display. The array substrate includes: a flexible base, and, a TFT and a connecting line which are on a side of the flexible base. The array substrate has a display area and a lead area. The TFT is in the display area. The connecting line is in the lead area. The connecting line is used to electrically connect the TFT to a drive circuit. A manufacturing material of the connecting line includes a flexible conductive material. Since the material forming the connecting line includes a flexible conductive material, and the flexible conductive material has electrical conductivity and is not easily broken, the breaking probability of the connecting line is reduced, and the yield of the display device is effectively improved.

Abstract: An object is to provide a technique capable of fixing a cover to a container body without using a dedicated fixation mechanism and fixation member. A semiconductor device includes: a container body having a space with an opening; a semiconductor element disposed in the space in the container body; a sealing member disposed in the space in the container body to cover the semiconductor element; and a cover covering the opening of the container body, wherein a convex portion protruding into the space is provided on the cover, and the cover is fixed to the container body only by embedding at least a tip portion of the convex portion in the sealing member which has been cured.

Abstract: A single photon avalanche diode (SPAD) image sensor is disclosed. The SPAD image sensor includes: a substrate having a front surface and a back surface; wherein the substrate includes a sensing region, and the sensing region includes: a common node heavily doped with dopants of a first conductivity type, the common node being within the substrate and abutting the back surface of the substrate; a sensing node heavily doped with dopants of a second conductivity type opposite to the first conductivity type, the sensing node being within the substrate and abutting the front surface of the substrate; and a first layer doped with dopants of the first conductivity type between the common node and the sensing node.

Abstract: Three-dimensional integrated circuit structures and methods of forming the same are disclosed. One of the three-dimensional integrated circuit structures includes a first die, a plurality of second dies and a dielectric structure. The second dies are bonded to the first die. The dielectric structure is disposed between the second dies. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer has a sidewall and a bottom, a first surface of the sidewall and a first surface of the bottom are in contact with the second dielectric layer and form a first angle. A second angle smaller than the first angle is formed by a second surface of the sidewall and a second surface of the bottom.

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.