Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.

Abstract: A pixel definition layer and a manufacturing method thereof, a display substrate, and a display panel are provided. The pixel definition layer includes: a lyophilic material layer on a base substrate, which includes a plurality of lyophilic portions spaced in pairs, which being with an annular structure and used to define a pixel region; and a lyophobic material layer on a side of the lyophilic material layer from the base substrate, which being filled between each two adjacent lyophilic portions of the plurality of lyophilic portions, and a distance from a surface of the lyophobic material layer from the base substrate to the base substrate is larger than a distance from a surface of the lyophilic material layer from the base substrate to the base substrate. The pixel definition layer improves the uniformity of films formed in the pixel region by the solution.

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of detecting electrical failure thereof. The three-dimensional semiconductor memory device includes a substrate with a first conductivity including a cell array region and an extension region having different threshold voltages from each other, a stack structure on the substrate and including stacked electrodes, an electrical vertical channel penetrating the stack structure on the cell array region, and a dummy vertical channel penetrating the stack structure on the extension region. The substrate comprises a pocket well having the first conductivity and provided with the stack structure thereon, and a deep well surrounding the pocket well and having a second conductivity opposite to the first conductivity.

Abstract: A reflective display device provided with an optical layer which is capable of improving adhesion between a substrate and a reflective layer and controlling a color of reflected light is disclosed. The reflective display device includes first and second substrates facing each other, each of which includes a display area and a reflective area; a display element provided in the display area; a reflective layer provided in the reflective area and arranged on one surface of the second substrate to reflect incident light; and an optical layer arranged between the second substrate and the reflective layer.

Abstract: A light-emitting device includes a substrate; a first light-emitting unit and a second light-emitting unit formed on the substrate, each of the first light-emitting unit and the second light-emitting unit includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; a trench formed between the first light-emitting unit and the second light-emitting unit, and exposing the substrate; and a connecting electrode including a first connecting part on the first light-emitting unit and connected to the first semiconductor layer of the first light-emitting unit, a second connecting part on the second light-emitting unit and connected to the second semiconductor layer of the second light-emitting unit, and a third connecting part formed in the trench to connect the first connecting part and the second connecting part.

Abstract: A device for guiding charge carriers and uses of the device are proposed, wherein the charge carriers are guided by means of a magnetic field along a curved or angled main path in a two-dimensional electron gas or in a thin superconducting layer, so that a different presence density is produced at electrical connections.

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

Abstract: A vertical memory device includes gate electrodes on a substrate and a first structure. The gate electrodes may be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction, and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs) therein.

Abstract: A quantum dot (QD) light emitting diode comprising first and second electrodes facing each other; a QD emitting material layer between the first and second electrodes; and a semiconducting member acting as a hole transporting path in the QD emitting material layer is provided.

Abstract: Aspects of this disclosure relate to a filter that includes an acoustic wave device with a multi-layer substrate with heat dissipation. The multi-layer substrate includes a support substrate (e.g., a quartz substrate), a piezoelectric layer, an interdigital transducer electrode on the piezoelectric layer, and a thermally conductive layer configured to dissipate heat associated with the acoustic wave device. The thermally conductive layer is disposed between the support substrate and the piezoelectric layer. The thermally conductive layer has a thickness that is greater than 10 nanometers and less than a thickness of the piezoelectric layer.

Abstract: A method for manufacturing a package includes: preparing a lead frame that, in a region where the package is to be formed, has first and second electrodes, and has a through-hole at a position that spans across outer edges of the region; clamping the first and second electrodes between upper and lower molding dies; injecting a first resin into the molding dies, through an injection opening formed adjacent to the first electrode and on the outside of the region, so that the first resin has a wall that constitutes a side wall of a bottomed concave component with an outer lead component protruding outward from the wall, and a height of the side wall is larger than a thickness of the outer lead component; curing or solidifying the injected first resin; and cutting out an injection mark by cutting the lead frame at the outer edges of the region.

Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

Abstract: Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.

Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.

Abstract: A package structure of a directly modulated laser in a photonics module includes a thermoelectric cooler including multiple conductor traces formed in a cool surface. The package structure further includes a directly modulated laser (DML) chip having a first electrode being attached with the cool surface and a second electrode at a distance away from the cool surface. Additionally, the package structure includes an interposer having a plurality of through-holes formed between a first surface to a second surface. The first surface is mounted to the cool surface such that each through-hole is aligned with one of the multiple conductor traces and the second surface being leveled with the second electrode. Moreover, the package structure includes a driver disposed on the second surface of the interposer with at least a galvanically coupled output port coupled directly to the second electrode of the DML chip.

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.