Abstract: The sensor package comprises a carrier (1) including electric conductors (13), an ASIC device (6) and a sensor element (7), which is integrated in the ASIC device (6). A dummy die or interposer (4) is arranged between the carrier (1) and the ASIC device (6). The dummy die or interposer (4) is fastened to the carrier (1), and the ASIC device (6) is fastened to the dummy die or interposer (4).

Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

Abstract: An embodiment of a transformer-based system or galvanic isolation device includes a first coil, a second coil aligned with the first coil across a gap, and a first capacitor coupled between the first coil and a first voltage reference. A first electrode of the first capacitor may be formed from a conductive electrode structure that is electrically isolated from the first coil, and a second electrode of the first capacitor may be formed from at least a portion of the first coil. The system or device also may include a second capacitor coupled between the second coil and a second voltage reference. The first and second coils may form portions of first and second IC die, respectively, and the system or device may also include one or more dielectric components within the gap between the IC die, where the dielectric component(s) are positioned directly between the first and second coils.

Abstract: A MEMS transducer system includes a MEMS transducer device for sensing at least one of pressure signal or acoustic signal. The MEMS transducer device includes first and second diaphragms. Formed between the diaphragms are a spacer, plate capacitor elements, and electrode elements. The plate capacitor elements are coupled to the diaphragms via the spacer. An optional member may be disposed within the spacer. The distal ends of the electrode elements are coupled to a structure such as insulator element. An optional oxides may be formed within the plate capacitor elements. Pressure sensing electrode formed between the diaphragms may be coupled to the insulator element.

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

Abstract: A flexible display panel is disclosed. The flexible display panel includes a substrate and a pixel unit on a first surface of the substrate. An encapsulation layer is on the first surface of the substrate and covers the pixel unit. A support member is on a second surface of the substrate that is opposite the first surface. The support member overlaps an edge of the encapsulation layer. The support member reduces stress applied to areas of the flexible display panel that are vulnerable to cracking during bending of the flexible display panel.

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the base region.

Abstract: A bidirectional Zener diode includes a substrate, a first conductivity type base region formed at a front surface portion of the substrate, a second conductivity type first impurity region formed at the base region, a second conductivity type second impurity region formed at the base region away from the first impurity region, an insulating layer formed on a front surface of the substrate, a first electrode film formed on the insulating layer and electrically connected to the first impurity region, and a second electrode film formed on the insulating layer and electrically connected to the second impurity region, and a first region formed on the insulating layer, the first region being sandwiched between the first electrode film and the second electrode film, and the first region including a portion having an aspect ratio of 1 or larger.

Abstract: The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.

Abstract: A laser apparatus may include a spectrum controller and a spectrum modulator. The spectrum controller may control a center wavelength and/or a bandwidth of a spectrum of a laser beam. The spectrum modulator may modulate the spectrum of the laser beam having the center wavelength and/or the bandwidth controlled by the spectrum controller. Thus, the laser beam may have the spectrum optimal for a semiconductor fabrication process. Particularly, the substrate may be accurately diced using the laser beam having the optimal spectrum.

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

Abstract: A method for arranging a plurality of semiconductor seed substrates on a carrier element, in which for applying a semiconductor layer to the seed substrates, the seed substrates are arranged on the carrier element by integral bonding. A carrier element having integrally bonded seed substrates for coating with a semiconductor layer is also provided.

Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, and depositing a first dielectric material on the first semiconductor fin and the second semiconductor fin on the semiconductor substrate using an atomic layer deposition process. There is a first trench between the first semiconductor fin and the second semiconductor fin. The method also includes filling the first trench with a flowable dielectric material, and heating the flowable dielectric material and the first dielectric material to form an isolation structure between the first semiconductor fin and the second semiconductor fin.

Abstract: In one embodiment, a multi-purpose sensor may couple to a machine operating in an industrial environment and include numerous sensors disposed within the multi-purpose sensor to acquire sets of data associated with the machine or an environment surrounding the machine. A first portion of the sets of data may include historical sensor measurements over time for each of the sensors, and a second portion of the sets of data may include sensor measurements subsequent to when the first portion is acquired for each of the sensors. A processor of the multi-purpose sensor may determine a baseline collective signature based on the first portion, determine a subsequent collective signature based on the second portion, determine whether the collective signatures vary, and generate signals when a variance exists. The signals may cause a computing device, a cloud-based computing system, and/or a control/monitoring device to perform various actions.

Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.

Abstract: Disclosed is a method of forming a doughnut-shaped skyrmion, the method including heating a local area of a vertical magnetic thin film magnetized in a first direction, which is any one of an upward direction and a downward direction, applying a magnetic field having a second direction, which is opposite the first direction, and having intensity higher than coercive force of the vertical magnetic thin film to the vertical magnetic thin film to form a first area magnetized in the second direction, applying a magnetic field having the second direction to the vertical magnetic thin film to form a second area, which is an extension of the first area, and applying a magnetic field having the first direction to the vertical magnetic thin film to form a third area magnetized in the first direction in the second area.

Abstract: A method of manufacturing a semiconductor laser including providing a substrate having a semiconductor layer sequence with an active layer that generates light during operation of the semiconductor laser, applying a continuous contact layer having at least one first partial region and at least one second partial region on a bottom side of the substrate opposite the semiconductor layer sequence, and locally annealing the contact layer only in the at least one first partial region.

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

Abstract: Methods and structures for forming epitaxial layers of Ill-nitride materials on patterned foreign substrates with low stacking fault densities are described. Semipolar and nonpolar orientations of GaN that are essentially free from stacking faults may be grown from crystal-growth facets of a patterned substrate. Etching can be used to remove stacking faults if present. Crystal growth with an impurity can eliminate crystal growth from a facet that is responsible for stacking fault formation and permit substantially stacking-fault-free growth of the Ill-nitride material.