Abstract: A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.

Abstract: A display unit includes a first electrode, an organic layer, and a second electrode. The first electrode, the organic layer, and the second electrode are provided in this order on a substrate. The organic layer includes a light-emitting layer. The second electrode includes, in order from the organic layer, a first electrically conductive film, a high-resistivity layer, and a second electrically conductive film. The first electrically conductive film is transparent and includes an insulated or ablated local part. The high-resistivity layer has higher electric resistance than the first electrically conductive film. The second electrically conductive film is provided on the high-resistivity layer.

Abstract: An electronic component mounting board reduces short-circuiting between a plurality of thick wiring conductors to improve reliability and electrical characteristics. An electronic component mounting board (1) includes a substrate (2) including a mount area (4) in which an electronic component (10) is mountable, a first insulating layer (2a) overlapping the mount area (4), a second insulating layer (2b) on a lower surface of the first insulating layer (2a), and a first metal layer (5) between the first insulating layer (2a) and the second insulating layer (2b).

Abstract: A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), IOFF represents the off-state current, t represents time during which the transistor is off, ? and ? are constants, ? is a constant that satisfies 0<??1, and CS is a constant that represents load capacitance of a source or a drain.

Abstract: A printed circuit board includes first and second insulating layers forming a cavity, a first heat releasing layer formed on an exterior surface of the cavity, and a circuit layer formed above or below the first the insulating layer and at least between a surface of the cavity and the first insulating layer. The heat releasing layer is electrically connected to at least a portion of the circuit layer.

Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

Abstract: Light emitting device includes structure protruding from a side of a surface of second conductive semiconductor layer of LED chip toward a side of a surface of second conductor portion of mounting substrate to contact the surface of second conductor portion, and is positioned to extend around an outer periphery of second electrode. First electrode and a first conductor portion are joined to each other by first joint portion, and second joint portion joining second electrode and second conductor portion to each other fills a space surrounded by second electrode, protruding structure, and second conductor portion. Protruding structure is disposed to extend around the outer periphery of second electrode to surround second joint portion in planar view. A part of mounting substrate overlapping protruding structure in planar view is either identical in height to or lower than a part of second conductor portion joined to second joint portion.

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract: A semiconductor device is provided, including: a semiconductor substrate having an active area and an edge termination region; an upper electrode; an insulating film provided between the semiconductor substrate and the upper electrode and having a contact hole; a first conductivity-type drift region; a second conductivity-type base region; a second conductivity-type well region; and a second conductivity-type extension region formed extending in a direction toward the well region from the base region and separated from the upper electrode by the insulating film, wherein a sum of a first distance from an end portion of the contact hole closer to the well region to an end portion of the extension region closer to the well region and a second distance from the end portion of the extension region closer to the well region to the well region is smaller than a thickness of the semiconductor substrate in the active area.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

Abstract: A package includes a first electrode, a second electrode, a wall, and a flange. The polarity of the second electrode is different from that of the first electrode, and at least one of the first electrode and the second electrode has an outer lead component that has a recess formed at a distal end. The wall fixes the first electrode and the second electrode, constitutes a side wall of a bottomed concave component in which at least part of a bottom surface of the bottomed concave component is constituted by the first electrode and the second electrode, and has the outer lead component protruded therefrom. The flange protrudes outward from the wall, and is provided with the same thickness as the outer lead component, on two sides of the outer lead component in plan view where the recess is not formed.

Abstract: A semiconductor device includes a semiconductor portion of a first conductivity type, a first semiconductor layer and a second semiconductor layer of a second conductivity type separated from each other and provided in an upper layer portion of the semiconductor portion, a gate electrode provided on the semiconductor portion, a first contact piercing the gate electrode, a second contact piercing the gate electrode, a first insulating film provided between the first semiconductor layer and a side surface of the first contact and between the first contact and the gate electrode, and a second insulating film provided between the second semiconductor layer and a side surface of the second contact and between the second contact and the gate electrode. A lower portion of the first contact is disposed inside the first semiconductor layer, a lower end of the first contact is connected to the first semiconductor layer.

Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.

Abstract: Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.