Abstract: A conductive pattern structure is provided by the embodiment of present disclosure. The conductive pattern structure includes: a first metal pattern and a second metal pattern. The second metal pattern covers at least a portion of a side surface of the first metal pattern; and an activity of a metal material of the first metal pattern is weaker than an activity of a metal material of the second metal pattern. The embodiment of present disclosure prevents the side surface of the first metal pattern from being oxidized by forming the second metal pattern covering at least a portion of the side surface of the first metal pattern, in this way, the problem that the electrical conductivity of the first metal pattern is reduced is avoided, and the problem that product yield declining is avoided.

Abstract: The present disclosure discloses a display panel including a flat layer, a mixed layer and a base film layer sequentially disposed; wherein the mixed layer includes an organic film layer and a multi-film structure, the organic film layer and the multi-film structure are alternately distributed on the base film layer in a direction parallel to the base film layer. In the present disclosure, the ability to omni-directionally bend a display panel is improved by replacing the inorganic film layer in a specific area below the flat layer of the display panel with an organic film layer to improve the omnibearing bending ability of the display panel and enhance the user experience.

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.

Abstract: Systems, methods and apparatus are provided for soil testing. In some embodiments, a soil sample quality criterion is determined and associated with the soil sample. In some embodiments a soil characteristic measurement is additionally taken and associated with the soil sample. In some embodiments, the soil sample and its associated data are associated with a container in which the soil sample is placed.

Abstract: A nitride semiconductor light emitting element includes a first nitride semiconductor layer of a first conductivity type, nitride semiconductor stacked bodies each of which is formed on a portion of the first nitride semiconductor layer and includes a nitride semiconductor light emitting layer and a second nitride semiconductor layer of a second conductivity type, first electrodes formed on the first nitride semiconductor layer, and second electrodes each of which is formed on the second nitride semiconductor layers of the nitride semiconductor stacked bodies. The first and the second electrodes extend in a first direction. The first and the second electrodes are arranged in parallel with one another with gaps interposed therebetween in a second direction perpendicular to the first direction in plan view. A dimension of first electrodes sandwiched by second electrodes is greater than a dimension of first electrodes not sandwiched by second electrodes in the second direction.

Abstract: A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a substrate including a separation area and a plurality of pixel formed over the substrate. The separation area is formed between adjacent pixels, and a plurality of through holes are respectively defined by a plurality of surrounding inner surfaces of the separation area, and wherein each of the inner surfaces passes through the substrate. The display device also includes an encapsulation layer formed over the substrate and covering the inner surfaces of the separation area.

Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. Microelectronic devices including first and second fins that are laterally offset by a fin pitch to define a first field there between are also described. In embodiments the microelectronic devices include a conformal oxide layer and a conformal nitride layer on at least a portion of the first and second fins, where the conformal nitride layer is on at least a portion of the conformal oxide layer and a sacrificial oxide material is disposed within the first field.

Abstract: A FinFET device structure and method for forming the same are provided. The Fin PET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.

Abstract: A nanostructured article having a first layer with a nanostructured surface is described. The nanostructured surface includes a plurality of pillars extending from a base surface of the first layer. The pillars have an average height greater than an average lateral dimension of the pillars. An average center-to-center spacing between pillars is no more than 2000 nm. The average lateral dimension is no less than 50 nm. Each pillar in the plurality of pillars has at least a lower portion and an upper portion where the lower portion is between the upper portion and the base surface, and the upper and lower portions have differing compositions. The nanostructured article includes a second layer disposed over the plurality of pillars and extending continuously to the base surface.

Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a substrate including a separation area and a plurality of pixel formed over the substrate. The separation area is formed between adjacent pixels, and a plurality of through holes are respectively defined by a plurality of surrounding inner surfaces of the separation area, and wherein each of the inner surfaces passes through the substrate. The display device also includes an encapsulation layer formed over the substrate and covering the inner surfaces of the separation area.

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.

Abstract: Briefly, in accordance with one embodiment, a transparent conductive structure and method to form such a structure are described. For example, an apparatus may include an optoelectronic device. In such an embodiment, an optoelectronic device may include one or more zinc oxide crystals forming a single contiguous three-dimensional transparent conductive structure. The single contiguous three-dimensional transparent conductive structure may include one or more regions thereof having one or more three dimensional geometrical features in the one or more regions of the single contiguous three-dimensional transparent conductive structure so that the single contiguous three-dimensional transparent conductive structure possesses additional electrical-type and/or optical-type properties. For example, additional electrical-type and/or optical-type properties may include electrical current management and/or light management properties.

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A light source module includes a heat sink having a mounting region; a light emitting device package having a first surface disposed on the mounting region of the heat sink and a second surface that is opposite to the first surface, the light emitting device package including a connection pad disposed on the second surface; a circuit board disposed on the mounting region of the heat sink and spaced apart from the light emitting device package, the circuit board including a connector and a terminal electrically connected to the connector; and a bracket disposed between the light emitting device package and the circuit board on the mounting region of the heat sink, and coupled to the heat sink, the bracket including a lead frame pressing the connection pad and the terminal to connect the connection pad and the terminal.

Abstract: A quantum-confined device (100) and method for manufacture thereof. The device (100) comprises a substrate (10) having at least one protrusion (12) and a layer of a two-dimensional material (14) arranged thereupon. The layer of the two-dimensional material (14) is arranged on the substrate (10) and the at least one protrusion (12), the at least one protrusion (12) causing localised strain in the layer of the two-dimensional material (14) to form a quantum dot or a quantum wire at the region of localised strain.

Abstract: Provided is a display apparatus, including a substrate; a plurality of pixels that are on the substrate and include at least one display device; a separation area that is on the substrate and between two adjacent pixels from among the plurality of pixels; and a penetrating portion that is in the separation area and penetrates the substrate.