Abstract: A method is described for identifying communication-ready data bus subscribers connected to a local bus. The method comprises receiving, at a local bus master, at least one data packet transmitted via the local bus, wherein the at least one data packet received at the local bus master comprises an address of a communication-ready data bus subscriber among a plurality of communication-ready data bus subscribers in the local bus, wherein the communication-ready data bus subscriber is in a sequence of communication-ready data bus subscribers, and mapping of the received address by the local bus master to a relative position of the communication-ready data bus subscriber in the sequence of communication-ready data bus subscribers in the local bus. In addition, a local bus master of the local bus is described.

Abstract: An arithmetic processing device includes a plurality of arithmetic processing circuitry, each of which includes: an instruction hold circuit configured to hold an arithmetic instruction; an arithmetic circuit configured to execute an arithmetic instruction issued from the instruction hold circuit; and a measurement circuit configured to measure a predetermined time period, wherein the instruction hold circuit is configured to perform first processing after the instruction hold circuit holds a first arithmetic instruction when the arithmetic circuit is not executing other arithmetic instructions, the first processing being configured to: cause the measurement circuit to initiate the measurement of the predetermined time; and issue, in response to a completion of the measurement of the predetermined time period, the held first arithmetic instruction to the arithmetic circuit, and wherein the predetermined time period measured by the measurement circuit is different between at least two of the plurality of arith

Abstract: Systems, methods, apparatuses, and computer program products for packet latency reduction in mobile radio access networks. One method may include, when a buffer of a first sublayer of a wireless access link is empty and there is a new data unit in the first sublayer or when the first sublayer buffer is not empty and a data unit leaves a second sublayer buffer, comparing the number of data units currently stored in the second sublayer buffer with a queue length threshold that defines a total amount of space in the second sublayer buffer. When the number of data units currently stored in the second sublayer buffer is less than the queue length threshold, the method may also include transferring the data unit from the first sublayer to the second sublayer.

Abstract: An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

Abstract: A heterogeneous bus bridge circuit and related apparatus are provided. The heterogeneous bus bridge circuit is configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses that are different from the RFFE bus. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). In examples discussed herein, the heterogeneous bus bridge circuit can be configured to selectively activate an auxiliary bus for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.

Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

Abstract: A device is provided having a communication interface and a Fountain code decoding unit, set up to reconstruct a configuration data record from a plurality of data packets received via the communication interface, wherein the device is set up to configure or to reconfigure itself using the reconstructed configuration data record.

Abstract: An apparatus and method for compressing floating-point values.

Abstract: A graphics processing unit includes a sparse matrix detection unit, a register file, an assertion register, and a matrix calculation unit. The sparse matrix detection unit reads a plurality of matrices from a storage device and determines whether the matrices are zero matrices or non-zero matrices to output a determination result. The register file stores the plurality of matrices from the sparse matrix detection unit. The assertion register marks up the matrices according to the determination result, and outputs a mark result. The matrix calculation unit receives a matrix calculation instruction, reads the non-zero matrices in the plurality of matrices from the register file according to the mark result, and calculates the non-zero matrices.

Abstract: In one embodiment, a system includes a memory and a processor core. The processor core includes functional units and an instruction decode unit configured to determine whether an execute packet of instructions received by the processing core includes a first instruction that is designated for execution by a first functional unit of the functional units and a second instruction that is a condition code extension instruction that includes a plurality of sets of condition code bits, wherein each set of condition code bits corresponds to a different one of the functional units, and wherein the sets of condition code bits include a first set of condition code bits that corresponds to the first functional unit. When the execute packet includes the first and second instructions, the first functional unit is configured to execute the first instruction conditionally based upon the first set of condition code bits in the second instruction.

Abstract: A retimer apparatus can include a receiver circuit implemented at least partially in hardware; a configuration register comprising a link management bit set, and one or more bit fields for link management bits indicating link management information; bit stream logic implemented at least partially in hardware to encode an ordered set (OS) with one or more link management bits from the configuration register; and a transmitter circuit implemented at least partially in hardware to transmit OS with the one or more link management bits across a link.

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described.

Abstract: A method of scheduling instructions in a processing system comprising a processing unit and one or more co-processors comprises dispatching a plurality of instructions from a master processor to a co-processor of the one or more co-processors, wherein each instruction of the plurality of instructions comprises one or more additional fields, wherein at least one field comprises grouping information operable to consolidate the plurality of instructions for decomposition, and wherein at least one field comprises control information. The method also comprises decomposing the plurality of instructions into a plurality of fine-grained instructions, wherein the control information comprises rules associated with decomposing the plurality of instructions into the plurality of fine-grained instructions. Further, the method comprises scheduling the plurality of fine-grained instructions to execute on the co-processor, wherein the scheduling is performed in a non-sequential order.

Abstract: Examples of the present disclosure relate to an apparatus comprising execution circuitry to execute instructions defining data processing operations on data items. The apparatus comprises cache storage to store temporary copies of the data items. The apparatus comprises prefetching circuitry to a) predict that a data item will be subject to the data processing operations by the execution circuitry by determining that the data item is consistent with an extrapolation of previous data item retrieval by the execution circuitry, and identifying that at least one control flow element of the instructions indicates that the data item will be subject to the data processing operations by the execution circuitry; and b) prefetch the data item into the cache storage.

Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication.

Abstract: Disclosed embodiments relate to a new instruction for performing data-ready memory access operations. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, at least one memory location identifier identifying at least one data element, a register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask, wherein the execution circuit is to, for each data element of the at least one data element, determine whether a memory request for the data element satisfies the at least one data access condition identified by the data readiness indicator, and in response to determining that the data access condition: generate a prefetch request for the data element, and set a value in a corresponding data element position of the data readiness mask to indicate that the memory request for the data element does not satisfy the at least one data access condition.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, performing a matrix operation of zeroing a matrix in response to a single instruction. For example, a processor detailed which includes decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.

Abstract: Provided are a two-dimensional data matching method, a device and a logic circuit. The method is executed by a first operator, a first queue, a second operator, a first counter, a second queue, a third operator, a second counter, a first comparator, and a first memory sequentially connected. The method includes: the first operator performs a bitwise matching operation on the matrix a and the matrix b row by row, inputting the result to the first queue; the second operator performs a cumulative operation on the matching result, and outputting an accumulative value to the second queue; the second operator performs a cumulative operation on the accumulative value, and inputs an accumulated result to the first comparator; the first comparator compares the accumulated result with a pre-stored matching threshold, and inputs the comparison result to the first memory to form a matching result matrix; and repeating the above steps.