Abstract: A Multi-I/O SPI for precision converters supports a Dual/Quad/Octal SPI to support the speed requirements for digital transmission and also includes a special mode that can be enabled by hardware and/or software to remove the bit scrambling requirement dictated by the JEDEC standard. The special mode removes the scramble requirement and associates each of the bidirectional data lines to a specific channel. The special mode provides backward compatibility that permits the precision converter to be used with controllers that do not natively support the JEDEC standard. Also, the Multi-I/O SPI includes registers divided into a primary region that is accessed only in default mode at power-up for write and/or read operations, and a secondary region that is accessed by any mode enabled in the control register. By restricting access to the “control” register area to a pre-defined mode in the converter at power-up, the access mode can be controlled.

Abstract: A system, processor, and/or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Instructions executed by the compute element include operand specifiers, some specifying a data structure register storing a data structure descriptor describing an operand as a fabric vector or a memory vector. The data structure descriptor further describes various attributes of the fabric vector: length, microthreading eligibility, number of data elements to receive, transmit, and/or process in parallel, virtual channel and task identification information, whether to terminate upon receiving a control wavelet, and whether to mark an outgoing wavelet a control wavelet.

Abstract: A processor includes at least one memory controller, and a decode unit to decode a persistent commit demarcate instruction. The persistent commit demarcate instruction is to indicate a destination storage location. The processor also includes an execution unit coupled with the decode unit and the at least one memory controller. The execution unit, in response to the persistent commit demarcate instruction, is to store a demarcation value in the destination storage location. The demarcation value may demarcate at least all first store to persistent memory operations that are to have been accepted to memory when the persistent commit demarcate instruction is performed, but which are not necessarily to have been stored persistently, from at least all second store to persistent memory operations that are not yet to have been accepted to memory when the persistent commit demarcate instruction is performed.

Abstract: Techniques for transmitting data may comprise: receiving a first data transfer rate indicating a communication rate at which a first entity communicates with a second entity over a communications fabric; receiving a second data transfer rate indicating a communication rate at which the second entity communicates with the first entity over the communications fabric; and performing first processing to send first data from the first entity to the second entity over the communications fabric, said first processing including: determining whether the first data transfer rate is greater than the second data transfer rate; and responsive to determining the first data transfer rate is greater than the second transfer rate, performing second processing by the first entity that controls and limits, in accordance with the second data transfer rate, a rate at which the first data is transmitted from the first entity to the second entity.

Abstract: A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.

Abstract: Methods and devices are described for charging a smart battery in a computing device. The methods and devices may include determining, by a battery management controller, a charging configuration for managing one or more battery modules of the smart battery and transmitting a charging configuration signal to one or more battery modules of the smart battery. The methods and devices may include receiving, by at least one of a plurality of charging coils, power from a wireless signal based on the wireless signal coupling energy to at least one of the plurality of charging coils at a frequency as the at least one of the plurality of charging coils and charging at least one battery module connected to a respective one of the plurality of battery control boards in response to a respective one of the plurality of charging coils receiving the power from the wireless signal.

Abstract: Embodiments of this application relate to a convolutional computing accelerator, a convolutional computing method, and a convolutional computing device, which belong to the technical field of electronic circuits. The convolutional computing accelerator includes: a controller, a computing matrix, and a first cache. The computing matrix comprising at least one row of computing units, each row of computing units comprising at least two adjacent connected computing units. The controller is configured to control input data of each row of computing units to be loaded into the first cache, and to control the input data loaded into the first cache to be inputted into the two adjacent computing units in a corresponding row. Each of the computing units in the corresponding row is configured to perform, in a first clock cycle, a convolutional computation based on received input data and a pre-stored convolutional kernel.

Abstract: Interactions between a classical computing system and a quantum computing system can be structured to increase the effective memory available to hold instructions for a quantum processor. The system stores a schedule of compiled quantum processing instructions in a memory storage location on a classical computing system. A small program memory is included in close proximity to a control system for the quantum processor on the quantum computing system. The classical computing system sends a subset of instructions from the schedule of quantum instructions to the program memory. The control system manages execution of the instructions by accessing them at the program memory and configuring the quantum processor accordingly. While the quantum processor executes the instructions, additional instructions are transferred from the classical computing system to the program memory to await execution.

Abstract: A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.

Abstract: The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first output and a second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system includes multiple multiplexing units and multiple data acquisition units receiving multiple data streams from multiple machines in the industrial environment.

Abstract: Method and apparatus for converting scatter control elements to gather control elements used to permute vector data elements is described herein. One embodiment of a method includes decoding an instruction having a field for a source vector operand storing a plurality of data elements, wherein each of the data element includes a set bit and a plurality of unset bits. Each of the set bits is set at a unique bit offset within the respective data element. The method further includes executing the decoded instruction by generating, for each bit offset across the plurality of data elements in the source vector operand, a count of unset bits between a first data element having a bit set at a current bit offset and a second data element comprising a least significant bit (LSB). A set of control elements is generated based on the count of unset bits generated for each bit offset.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

Abstract: A system and method of processing instructions may comprise an application processing domain (APD) and a metadata processing domain (MTD). The APD may comprise an application processor executing instructions and providing related information to the MTD. The MTD may comprise a tag processing unit (TPU) having a cache of policy-based rules enforced by the MTD. The TPU may determine, based on policies being enforced and metadata tags and operands associated with the instructions, that the instructions are allowed to execute (i.e., are valid). The TPU may write, if the instructions are valid, the metadata tags to a queue. The queue may (i) receive operation output information from the application processing domain, (ii) receive, from the TPU, the metadata tags, (iii) output, responsive to receiving the metadata tags, resulting information indicative of the operation output information and the metadata tags; and (iv) permit the resulting information to be written to memory.

Abstract: A predetermined field of a fetched instruction is extended to secure an instruction type and an operand length. An instruction conversion table stores an extension field longer than the predetermined field in association with a bit pattern of the predetermined field of an instruction. An extension field acquisition unit acquires the extension field by referring to the instruction conversion table, with a bit pattern of the predetermined field of the fetched instruction. An instruction decoder performs a decoding process on a new instruction including the extension field in place of the predetermined field of the fetched instruction.

Abstract: An apparatus has processing circuitry to execute a sequence of instructions, an integer storage element to store an integer value for access by the processing circuitry, and a capability storage element for storing a capability for access by the processing circuitry. A capability usage storage is then used to store capability usage information. The processing circuitry is responsive to execution of at least one instruction in the sequence of instructions to generate, in dependence on the capability usage information, a result to be stored in a destination storage element, when the capability usage information identifies a capability state, the result is generated as a capability, and the capability storage element is selected as the destination storage element, and when the capability usage information identifies a non-capability state, the result is generated as an integer value, and the integer storage element is selected as the destination storage element.

Abstract: A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.

Abstract: A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.

Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.