Abstract: A method can be used for addressing a slave integrated circuit connected to a bus. The slave integrated circuit has a default address on the bus. The method includes receiving, at the slave integrated circuit, an addressing message conveyed on the bus. The addressing message contains a replacement address. The method also includes replacing the default address within the slave integrated circuit with the replacement address upon receiving the addressing message, restarting the slave integrated circuit, and upon the restarting, assigning the replacement address as a new default address.

Abstract: A computer processor includes an issue queue to receive an instruction, and one or more execution units to generate a condition code bit corresponding to the instruction. A branch condition queue is in signal communication with the issue queue, and receives the instruction from the issue queue before the at least one execution unit generates the condition code bit.

Abstract: An interconnection system including a first gating unit and a second gating unit is provided. The first gating unit includes two terminals, with one terminal connecting to a first CPU directly, where the two terminals are indirectly connected when the first gating unit is in a first state. The second gating unit includes two terminals, with one terminal connecting to a second CPU, where the two terminals are connected when the second gating unit is in the first state. Another terminal of the first gating unit is connected to another terminal of the second gating unit. If both the first gating unit and the second gating unit are in the first state, the first CPU is connected to the second CPU.

Abstract: A method and apparatus generates control information that indicates whether to change a counter value associated with a particular load instruction. In response to the control information, the method and apparatus causes a hysteresis effect for operating between a speculative mode and a non-speculative mode based on the counter value. The hysteresis effect is in favor of the non-speculative mode. The method and apparatus causes the hysteresis effect by incrementing the counter value associated with the particular load instruction by a first value or decrementing the counter value by a second value. The first value is greater than the second value.

Abstract: Apparatus and a method of operating the same is disclosed. Instruction fetch circuitry is provided to fetch a block of instructions from memory and branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions. The branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a subsequent branch status indicator. When there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken the subsequent branch status indicator has a first value, and otherwise the subsequent branch status indicator has a second value. This supports improved handling of a misprediction as taken.

Abstract: An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

Abstract: An apparatus and method are provided for controlling a change in instruction set. The apparatus has processing circuitry arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry. A program counter capability storage element is used to store a program counter capability used by the processing circuitry to determined a program counter value. The processing circuitry is arranged to employ a capability based operation to change the instruction set. In response to execution of at least one type of instruction to load an identified capability into the program counter capability storage element, the processing circuitry is arranged to invoke the capability based operation in order to perform a capability check operation in respect of the identified capability, and to cause the instruction set to be identified by an instruction set identifier field from the identified capability provided the capability check operation is passed.

Abstract: This application discloses a data flow control method and apparatus. The method includes: calculating, by a device when a clock signal arrives, a quantity of transition-minimized differential signaling (TMDS) characters currently stored in a buffer of the device; and outputting, by the device, the TMDS character in the buffer when the quantity of TMDS characters currently stored in the buffer reaches a preset value, or outputting a gap data packet when the quantity of TMDS characters currently stored in the buffer does not reach a preset value, where the preset value is less than or equal to a TMDS character storage capacity of the buffer.

Abstract: Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described.

Abstract: The present application relates to a circuit and a transceiver comprising the circuit. The circuit comprises two bus line terminals for coupling to a bus and a bridge circuit comprising two legs. Each leg comprises an adjustable pull resistance and an adjustable push resistance connected in series with a respective one of the two bus line terminals. The adjustable pull resistances and the adjustable push resistances of the bridge circuit enable to independently adjust a driver impedance and to independently adjust a differential driver voltage on the bus. The circuit may further comprise an edge detector is coupled to a transmit data input and configured to detect a transition on the transmit data input and to adjust the impedances of the adjustable pull resistances and the adjustable push resistances in response to the detected transition.

Abstract: A data processing method comprises: if detecting that a number of image data to be transferred is greater than zero wherein the number of image data is a product of a number of input image data and a number of output image data, and a first available storage space of a FIFO memory is greater than or equal to a storage space occupied by an N number of input image data, transferring the N input image data in a first memory to the first FIFO memory; if detecting that a number of weight data to be transferred is greater than zero wherein the number of weight data is a product of the number of input image data and the number of output image data, and a second available storage space of a second FIFO memory is greater than or equal to a storage space occupied by an M number of weight data, transferring the M weight data in a second memory to the second FIFO memory; when the number of input image data cached in the first FIFO memory and the number of weight data cached in the second FIFO memory are greater than or e

Abstract: A processor includes a branch target buffer (BTB) having a plurality of entries whereby each entry corresponds to an associated instruction pointer value that is predicted to be a branch instruction. Each BTB entry stores a predicted branch target address for the branch instruction, and further stores information indicating whether the next branch in the block of instructions associated with the predicted branch target address is predicted to be a return instruction. In response to the BTB indicating that the next branch is predicted to be a return instruction, the processor initiates an access to a return stack that stores the return address for the predicted return instruction. By initiating access to the return stack responsive to the return prediction stored at the BTB, the processor reduces the delay in identifying the return address, thereby improving processing efficiency.

Abstract: A method and system of the branch look-ahead (BLA) instruction disassembling, assembling, and delivering are designed for improving speed of branch prediction and instruction fetch of microprocessor systems by reducing the amount of clock cycles required to deliver branch instructions to a branch predictor located inside the microprocessors. The invention is also designed for reducing run-length of the instructions found between branch instructions by disassembling the instructions in a basic block as a BLA instruction and a single or plurality of non-BLA instructions from the software/assembly program. The invention is also designed for dynamically reassembling the BLA and the non-BLA instructions and delivering them to a single or plurality of microprocessors in a compatible sequence. In particular, the reassembled instructions are concurrently delivered to a single or plurality of microprocessors in a timely and precise manner while providing compatibility of the software/assembly program.

Abstract: A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.

Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

Abstract: Data is supplied in a circular manner and overlapping memory accesses is suppressed in a processor. The processor includes a circular buffer and an instruction executing part. The circular buffer has a function of holding a plurality of pieces of data and reading the plurality of pieces of data in circulation. The instruction executing part executes an instruction that designates the circular buffer as an operand. That is, this processor has an instruction that designates the circular buffer as an operand, as an instruction set. With this configuration, the data is supplied in a circular manner from the circular buffer in the execution of the instruction by the processor.

Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described.

Abstract: Embodiments are disclosed for automated evaluation of compatibility of a data structure with a user device. An example method includes receiving, by communications circuitry, a set of user device characteristics regarding the user device, and retrieving, by the personalization circuitry, a set of data structure characteristics regarding the data structure. The example method further includes calculating, by the personalization circuitry, a set of characteristic-level compatibility scores, and generating, by the personalization circuitry and based on the set of characteristic-level compatibility scores, a compatibility score for the data structure and the user device. Subsequently, the example method includes generating, by an aggregator and using the generated compatibility score, an indication of relative compatibility of the data structure for the user device, and causing transmission, by communications circuitry, of a control signal to the user device based on the indication of relative compatibility.

Abstract: Methods, systems and apparatuses for performing walk operations of single instruction, multiple data (SIMD) instructions are disclosed. One method includes initiating, by a scheduler, a SIMD thread, where the scheduler is operative to schedule the SIMD thread. The method further includes fetching, a plurality of instructions for the SIMD thread. The method further includes determining, by a thread arbiter, at least one instruction that is a walk instruction, where the walk instruction iterates a block of instructions for a subset of channels of the SIMD thread, where the walk instruction includes a walk size, and where the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in a walk iteration in association with the walk instruction. The method further includes executing the walk instruction based on the walk size.

Abstract: A computer-controlled motorized pump system is provided. A generator is mechanically connected to a power takeoff. A first controller receives AC power from the generator and converts the AC power to DC power and provides DC power to a computing system that has one or more processors and one or more computer-readable hardware storage media and a user interface. A second controller is directly coupled to the first controller and provides AC power to a motor. The motor is mechanically connected to a pump, and the motor is in communication with, or controlled by, the computing system.