Abstract: A package structure including an integrated fan-out package and plurality of conductive terminals is provided. The integrated fan-out package includes an integrated circuit component, a plurality of conductive through vias, an insulating encapsulation having a first surface and a second surface opposite to the first surface, and a redistribution circuit structure. The insulating encapsulation laterally encapsulates the conductive through vias and the integrated circuit component. Each of conductive through vias includes a protruding portion accessibly revealed by the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit component and covers the first surface of the insulating encapsulation and the integrated circuit component.

Abstract: Provided are an organic light-emitting display panel and a display device. The organic light-emitting display panel includes: a display area; an organic light-emitting component located in the display area; a pixel defining layer located in the display area and including an aperture region defining the organic light-emitting component; a color resist layer located at a light-emitting side of the organic light-emitting component. The color resist layer includes a color resist corresponding to the aperture region, and a black resist located outside of the color resist in the display area. The color resist has a same color as the color of the organic light-emitting component corresponding to the corresponding aperture region.

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

Abstract: A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.

Abstract: An OLED device and a method of manufacturing the same, the OLED device including a substrate having a pixel area and a transmission area; a pixel circuit on the pixel area; a first electrode on the pixel area and being electrically connected to the pixel circuit; a first organic layer extending continuously on the pixel area and the transmission area and covering the first electrode; an emitting layer selectively on a portion of the first organic layer on the pixel area; a second organic layer extending continuously on the pixel and transmission areas and covering the emitting layer; and a third organic layer selectively on the transmission area, the third organic layer including a non-emitting material that has a different transmittance from that of the emitting layer; and a second electrode extending continuously on the pixel area and the transmission area and covering the second and third organic layers.

Abstract: The present invention provides a laminated member that prevents contact of a semiconductor chip and an external leading terminal etc. without increasing the number of components. The laminated member is a laminated member having a three-layer structure, comprising: an upper highly thermally conductive layer; a lower highly thermally conductive layer; and an intermediate layer having a low thermal expansion coefficient, wherein the above-described laminated member is larger than the above-described semiconductor chip in a plan view, and wherein a height position of the above-described first peripheral edge area is located at a certain distance below a height position of the above-described first bonding area, and a height position of the second peripheral edge area of the above-described second bonding area is located at a certain distance above a height position of the above-described second bonding area.

Abstract: Provided are electronic devices having a two-dimensional (2D) material layer. The electronic device includes an electrode layer that directly contacts an edge of the 2D material layer. The electrode layer may include a conductive material having a high work function or may have a structure in which an electrode layer includes a conductive material having a high work function and an electrode layer includes a conductive material having a low work function.

Abstract: Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.

Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.

Abstract: A semiconductor device may include an active fin, an element isolation film on a lower portion of the active fin and a gate structure crossing over the active fin. The gate structure may include first and second sides. The device may also include a source region and a drift region adjacent the first and second sides of the gate structure, respectively. The drift region may have a first impurity concentration. The device may further include a drain region that is in the drift region and may have a second impurity concentration higher than the first impurity concentration, a first trench that is in the drift region and may have a depth less than a height of the active fin, and an upper embedded insulating layer in the first trench. The gate structure may overlap a portion of the drift region and a portion of the first trench.

Abstract: A package (e.g., a wafer level package (WLP)) including one or more redistribution layers to fan out the contact pads of the one or more dies within an integrated circuit structure. An example package includes a die having a contact pad exposed at a frontside thereof. The package also includes a redistribution layer disposed over the frontside of the die. The redistribution layer includes metallization extending through a nano-composite material, which may be formed from a dielectric material with a nano-filler material disposed therein. The metallization is electrically coupled to the contact pad of the die. By incorporating the nano-composite material in the redistribution layer, the coefficient of thermal expansion (CTE) of the redistribution layer more closely matches the CTE of the die, which prevents or eliminates undesirable warpage of the redistribution layers.

Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.

Abstract: An optoelectronic semiconductor device and an apparatus with an optoelectronic semiconductor device are disclosed. In an embodiment the optoelectronic semiconductor component has an emission region including a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer, and an active region arranged between the first semiconductor layer and the second semiconductor layer for generating radiation, and a protection diode region. The semiconductor component has a contact for electrically contacting the semiconductor component externally. The contact has a first contact region that is connected to the emission region in an electrically conductive manner. The contact has further a second contact region that is spaced apart from the first contact region and connected to the protection diode region in an electrically conductive manner. The first contact region and the second contact region can be electrically contacted externally by a mutual end of a connecting line.

Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

Abstract: In a method of manufacturing a semiconductor device, a Schottky electrode is formed on an upper surface of a semiconductor substrate. A second region of the semiconductor substrate is etched such that a first region becomes higher than a second region, a rising surface is formed between the first and second regions, and an outer peripheral edge of the Schottky electrode is located on the first region. An insulating film is formed on the upper surface of the semiconductor substrate such that the insulating film annularly extends along the rising surface. A field plate electrode is formed. The field plate electrode is electrically connected with the Schottky electrode and faces the upper surface of the semiconductor substrate via the insulating film within an area extending from the outer peripheral edge of the Schottky electrode to the second region over the rising surface.

Abstract: Optoelectronic devices and method of forming the same include an optoelectronic component in a substrate layer. An integrated circuit chip is positioned on the substrate layer. A lens is positioned on the substrate layer directly above the optoelectronic component and above at least part of the integrated circuit chip. The lens has a cut-out portion that accommodates the integrated circuit chip.

Abstract: A semiconductor device includes: an n+ type of silicon carbide substrate, an n? type of layer, first trenches, a p type of region, a p+ type of region, an n+ type of region, a gate electrode, a source electrode, and a drain electrode.

Abstract: The present application provides an array substrate, which comprises a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, a plurality of pixel electrodes, and a plurality of conductive members. In each of the pixel regions, a control terminal of the TFT is electrically connected with the gate line, an input terminal of the TFT is electrically connected with the data line, and an output terminal of the TFT is electrically connected with the pixel electrode. The output terminal comprises a body, and a first contact and a second contact which are connected with the body. The first contact and one of the conductive members extending into the pixel region are overlapping-disposed and insulated from each other. The second contact and another of the conductive members extending into the pixel region are overlapping-disposed and insulated from each other.