Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region. Each of the well pick-up region and the active region includes a first well region and a second well region that have different conductivity types. There is a well boundary between the first well region and the second well region. A first fin structure is in the first well region of the well pick-up region and second fin structures are in the first well region of the active region. The minimum distance between the well boundary and the first fin structure is greater than the minimum distance between the well boundary and one of the second fin structures that is closest to the well boundary.

Abstract: The disclosure generally relates to a deoxyribonucleic acid (DNA) sequencing circuit having a controllable pore size and a lower membrane capacitance and noise floor relative to biological nanopore devices. For example, design principles used to fabricate a fin-shaped field effect transistor (FinFET) may be applied to form, on a first wafer, a nanopore that has a desired pore size in a silicon-based membrane. Electrodes and an interconnect embedded with an amplifier and analog-to-digital converter (ADC) may be formed on a separate second wafer, wherein the first wafer and the second wafer may then be bonded and further processed to form a sensing device that includes appropriate wells and pores to be used in a DNA sequencing circuit.

Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes forming a first composite structure, including a plurality of first composite layers, on a substrate, and forming a second composite structure, including a plurality of second composite layers on a surface portion of the first composite structure. The method also includes forming a first mask layer covering a sidewall of the second composite structure and a surface portion of the first composite structure and exposing at least another surface portion of the first composite structure. In addition, the method includes forming a second mask layer, on a surface portion of the second composite structure and spaced apart from the first mask layer by a first annular opening. Further, the method includes etching a top first layer of the first composite layers and a top first layer of the second composite layers.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device may include a first sensor configured to sense light having a wavelength within a first wavelength range from incident light and generates a first electrical signal based on the sensed light and a second sensor configured to sense light having a wavelength within a second, different wavelength range from the incident light and generates a second electrical signal based on the sensed light. The first and second sensors may be electrically connected to each other via an intermediate connector, and the first sensor and the second sensor may share a pixel circuit that is electrically connected thereto via the intermediate connector. The first and second wavelength ranges may include infra-red and visible wavelength ranges, respectively. The first and second wavelength ranges may include different visible wavelength ranges.

Abstract: The present disclosure provides a packaging adhesive, a packaging method, a display panel, and a display device. The packaging adhesive includes a frit, an organic solvent, and a material with a thermal expansion coefficient larger than that of the frit. Using the packaging adhesive provided by the present disclosure, the thermal expansion coefficient of the packaging adhesive from which the organic solvent is removed may be enhanced by doping the material with a thermal expansion coefficient larger than that of the frit into existing glass cement, so that in a packaging process using laser radiation, an expansion volume of the packaging adhesive when heated is increased. In this way, a gap between the packaging adhesive and an array substrate is effectively reduced, and a packaging effect is improved.

Abstract: An electronic assembly that includes a substrate having an aperture which extends through the substrate. The electronic assembly further includes a gull wing electronic package that includes leads which are solder mounted to the substrate such that the gull wing electronic package is within the aperture in the substrate, wherein the aperture is concentric with an exterior of the gull wing electronic package.

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

Abstract: An MTJ structure having vertical magnetic anisotropy is provided. The MTJ structure having vertical magnetic anisotropy can comprise: a substrate; an artificial antiferromagnetic layer located on the substrate; a buffer layer located on the artificial antiferromagnetic layer, and including W or an alloy containing W; a first ferromagnetic layer located on the buffer layer, and having vertical magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer, and having vertical magnetic anisotropy. Accordingly, in the application of bonding the artificial antiferromagnetic layer with a CoFeB/MgO/CoFeB structure, the MTJ structure having improved thermal stability at high temperature can be provided by using the buffer layer therebetween.

Abstract: Substrates, assemblies, and techniques for enabling a p-channel oxide semiconductor. For example, some embodiments can include an oxide semiconductor, where the oxide semiconductor includes an indium gallium zinc oxide (IGZO) sulfur alloy as a semiconducting material. The semiconducting material can be included in a thin-film-transistor that includes one or more p-channels.

Abstract: A semiconductor package device includes a leadframe, a first die and a package body. The leadframe includes a first die paddle and a lead. The first die paddle has a first surface and a second surface opposite to the first surface. The first die is disposed on the first surface of the first die paddle. The package body covers the first die and at least a portion of the first surface of the first die paddle and exposing the lead. The package body has a first surface and a second surface opposite to the first surface. The second surface of the package body is substantially coplanar with the second surface of the first die paddle. The lead extends from the second surface of the package body toward the first surface of the package body. A length of the lead is greater than a thickness of the package body.

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Abstract: The present invention relates to the field of semiconductor switches, and relates more particularly to a GaN-based bidirectional switch device. The present invention provides a gate-controlled tunneling bidirectional switch device without Ohmic-contact, which avoids a series of negative effects (such as current collapse, incompatibility with traditional CMOS process) caused by the high temperature ohm annealing process. Each insulated gate structure near schottky-contact controls the band structure of the schottky-contact to change the working state of the device, realizing the bidirectional switch's ability of bidirectional conducting and blocking. Due to the only presence of schottky in this invention, no heavy elements such as gold is needed, and this device is compatible with traditional CMOS technology.

Abstract: An image sensor comprises a first photodiode and a second photodiode having a smaller full-well capacitance than the first photodiode, wherein the second photodiode is adjacent to the first photodiode; a first micro-lens is disposed above the first photodiode and on an illuminated side of the image sensor; a second micro-lens is disposed above the second photodiode and on the illuminated side of the image sensor; and a coating layer disposed on both the first and second micro-lens, wherein the coating layer forms a flat top surface on the second micro-lens and a conformal coating layer on the first micro-lens.

Abstract: A semiconductor device includes a first contact positioned on an externally accessible surface of the semiconductor device and electrically coupled with a first structure in the semiconductor device, a second contact positioned on an externally accessible surface and electrically coupled with a second structure in the semiconductor device, and an isolation structure disposed between the first contact and the second contact, the isolation structure self-aligning with a first surface of the first contact such that the first surface of the first contact is orthogonal to the externally accessible surface up to a depth and faces the second contact.

Abstract: A qubit device includes an elongated thin film uninterrupted by Josephson junctions, a quantum device in electrical contact with a proximal end of the elongated thin film, and a ground plane that is co-planar with the elongated thin film and is in electrical contact with a distal end of the elongated thin film, in which the thin film, the quantum device, and the ground plane comprise a material that is superconducting at a designed operating temperature.

Abstract: Provided is a capacitor that has good bonding between the dielectric layer and the conductive layer, has a characteristic of low ESR, and keeps leak current suppressed. The capacitor contains a dielectric layer and a conductive film and is characterized in that the dielectric layer contains an organic compound and a metal compound and that the conductive film contains a conductive material and an organic compound.

Abstract: An LED chip includes a carrier, a semiconductor layer sequence, a reflective layer sequence arranged in regions between the carrier and the semiconductor layer sequence, wherein the reflective layer sequence includes a dielectric layer facing the semiconductor layer sequence and a metallic mirror layer facing away from the semiconductor layer sequence, and an encapsulating layer arranged in places between the carrier and the reflective layer sequence, the encapsulating layer extending in places through the reflective layer sequence into the semiconductor layer sequence and thus forming a separating web separating an inner region of the reflective layer sequence from an edge region of the reflective layer sequence.