Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.

Abstract: A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.

Abstract: A semiconductor device that can retain data for a long time is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor contains an oxide semiconductor in a channel formation region. The second transistor includes a first gate and a second gate. A gate of the first transistor is connected to a first electrode of the first transistor. The first electrode of the first transistor is connected to the second gate. A negative potential is applied to a second electrode of the first transistor. The first electrode and the second electrode of the first transistor include a first end portion and a second end portion, respectively. The first end portion and the second end portion face each other. The first end portion includes a first arc and the second end portion includes a second arc when seen from the top. The radius of curvature of the second arc is larger than that of the first arc.

Abstract: A flexible dielectric substrate (102) defines a LESD mounting region (120) including two conductive filled vias (105, 106) extending through the flexible dielectric substrate (102) and the LESD mounting region is substantially surrounded by two conductive frame portions (112, 116). The frame portions are in electrical connection with the conductive filled vias (105, 106), respectively. The conductive filled vias (105, 106) form conductive features in the mounting region (120) that are co-planar with each other.

Abstract: A method for forming a microelectromechanical device is shown. The method comprises forming a cavity in a semiconductor substrate material, wherein the semiconductor substrate material comprises an opening for providing access to the cavity through a main surface area of the semiconductor substrate material. In a further step, the method comprises forming a support structure having a support structure material different from the semiconductor substrate material to close the opening at least partially by mechanically connecting the main surface area of the semiconductor substrate material with the bottom of the cavity. Furthermore, the method comprises a step of forming a lamella structure in the main surface area above the cavity such that the lamella structure is held spaced apart from the bottom of the cavity by the support structure.

Abstract: Apparatus and method associated with surface structures of compute component packages are disclosed herein. In embodiments, an apparatus may include a plurality of structures provided on a surface of a compute component package, wherein the plurality of structures are to be used to attach and electrically couple the compute component package to another device, and wherein a structure of the plurality of structures includes first and second portions, the second portion disposed further from the surface than the first portion, and the first portion to comprise a material different from the second portion.

Abstract: A stacked complementary metal oxide semiconductor (CMOS) image sensor includes: a first semiconductor chip in which a plurality of pixels are in an upper area in a two-dimensional array structure and a first wiring layer is in a lower area; and a second semiconductor chip in which a second wiring layer is arranged in an upper area and logic elements are in a lower area, wherein the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer, and wherein a metal-insulator-metal (MIM) capacitor is in at least one of the first pad insulating layer and the second pad insulating layer.

Abstract: A leadframe has a peripheral frame. A die attach pad (DAP) is positioned inwardly and downwardly of the peripheral frame. Two spaced apart parallel arms engage one side of the DAP. In one embodiment the arms are portions of a U-shaped strap.

Abstract: The present invention provides a method for crystallizing a metal oxide semiconductor layer, a semiconductor structure, a method for manufacturing a semiconductor structure, an active array substrate, and an indium gallium zinc oxide crystal. The crystallization method includes the following steps: forming an amorphous metal oxide semiconductor layer on a substrate; forming an oxide layer on the amorphous metal oxide semiconductor layer; forming an amorphous silicon layer on the oxide layer; and irradiating the amorphous silicon layer by using a laser, so as to heat the amorphous silicon layer, where the heated amorphous silicon layer heats the amorphous metal oxide semiconductor layer, so that the amorphous metal oxide semiconductor layer is converted into a crystallized metal oxide semiconductor layer.

Abstract: Disclosed are an array substrate and a method for manufacturing the same, which belong to the technical field of display, and are able to solve the technical problem that the existing process for manufacturing array substrates is too complex. The array substrate includes a plurality of sub-pixel units formed on a base substrate. Each of the sub-pixel units comprises a thin film transistor and a second pixel electrode. An active layer of the thin film transistor is made of an oxide semiconductor. The second pixel electrode is made of a plasma treated transparent oxide semiconductor. The array substrate provided by the present disclosure can be used in an IPS or FFS liquid crystal display device.

Abstract: The present disclosure relates to the field of display, in particular to a composite cover film and a flexible display device. The composite cover film comprises a polyimide layer, and a first hard coating and a first transparent optical adhesive layer disposed on two sides of the polyimide layer, respectively, wherein at least one of the first hard coating and the first transparent optical adhesive layer contains a nanoscale colorant. The present disclosure further relates to a flexible display device comprising a flexible display panel and the composite cover film disposed on a light-exiting side of the flexible display panel.

Abstract: The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) (1) is configured of single crystal silicon and a handle substrate (second layer) (2) is configured of a material that has a higher thermal conductivity than the first layer. A heat dissipation substrate of the present invention has high heat dissipation properties.

Abstract: A display substrate, a method of fabricating the same and a display device are provided. The display substrate includes a substrate and a groove formed on the substrate. The groove is formed by photoresist and the bottom surface of the groove exceeds a height of a pixel area.

Abstract: An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.

Abstract: An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the antifuse, the antifuse has a low resistance. The antifuse may have a single breakdown point or multiple breakdown points. The antifuse includes a metal or metal alloy structure that is separated from a doped semiconductor material portion of the semiconductor substrate by an antifuse dielectric material liner. The metal or metal alloy structure and the antifuse dielectric material liner have topmost surfaces that are coplanar with each other as well as being coplanar with a topmost surface of the semiconductor substrate.

Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral region, and a first silicide layer on the substrate adjacent to the thyristor on the cell region. Preferably, the thyristor includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region, vertical dielectric patterns in the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and first contact plugs on the fourth semiconductor layer.

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

Abstract: A spin current magnetization reversal element includes: a first ferromagnetic metal layer with a changeable magnetization direction; and a spin-orbit torque wiring, wherein a first direction is perpendicular to a surface of the layer, the wiring extends in a second direction intersecting the first and is bonded to the layer, wherein the wiring material is a binary alloy represented by the formula AxB1-x, a metal carbide, or metal nitride, wherein A is selected from Al, Ti, and Pt, and B is selected from Al, Cr, Mn, Fe, Co, Ni, Y, Ru, Rh, and Ir and the material has a cubic structure with symmetry of a space group Pm-3m or Fd-3m; or A is selected from Al, Si, Ti, Y, and Ta, and B is selected from C, N, Co, Pt, Au, and Bi and the material has a cubic structure with symmetry of a space group Fm-3m.