Patents Examined by Steven H. Rao
  • Patent number: 8158474
    Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: April 17, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Min Cao, Chung-Te Lin, Ta-Ming Kuan, Cheng-Tung Hsu
  • Patent number: 8101467
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: January 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Patent number: 8053858
    Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: November 8, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 8039921
    Abstract: A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: October 18, 2011
    Assignee: NEC Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi
  • Patent number: 8030687
    Abstract: Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alberto Escobar, Brian J. Greene, Edward J. Nowak
  • Patent number: 8022409
    Abstract: A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patterns are formed each in a trench structure and extending from a storage node contact junction region to a channel region Line type gate patterns, each filling a predetermined portion of the trench of the individual recess pattern, is formed in a direction crossing a major axis of the active region in an upper portion of the individual channel region.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: September 20, 2011
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Sang-Man Bae
  • Patent number: 8022431
    Abstract: An illuminating apparatus has a reduced number of mounting spots by soldering or the like to permit an increased yield rate and a reduced cost. The illuminating apparatus has light emitting diodes, lead frames, and a transparent sealer. N light emitting diodes, N sets of lead frames mounted with the N light emitting diodes, and one set or more of lead frames each not mounted with a light emitting diode are sealed by the transparent sealer for integration into a modular illuminating apparatus. Also provided are a method for fabricating the illuminating apparatus, and a display apparatus using the illuminating apparatus.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: September 20, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hiroki Kaneko, Ikuo Hiyama, Toshiaki Tanaka, Masaya Adachi, Tsunenori Yamamoto, Haruo Akahoshi
  • Patent number: 8004021
    Abstract: Microfabricated devices for operation in a fluid that include a substrate that has a first and second surface and a first electrode material layer located over the first surface of the substrate. The devices have a piezoelectric material layer located over the first electrode material layer and a second electrode material layer located over the piezoelectric material layer. The devices also include a layer of isolation material located over the second electrode material layer that at least one of chemically or electrically isolates a portion of the second electrode material layer from a fluid. Some devices include a layer of conductive material located over the layer of isolation material.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: August 23, 2011
    Assignee: BioScale, Inc.
    Inventors: Michael F. Miller, Shivalik Bakshi
  • Patent number: 8004019
    Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: August 23, 2011
    Assignee: Sony Corporation
    Inventors: Hiroaki Fujita, Ryoji Suzuki, Nobuo Nakamura, Yasushi Maruyama
  • Patent number: 8003987
    Abstract: In order to suppress the effect due to electrons (holes) generated by incident light that cannot be prevented from entering only by means of light shielding, rather than the drain region 34 of a transistor, with respect to a majority carrier, a region 36 whose voltage is set to a value lower than the reference value of product of the voltage of a drain region and Q (unit electric charge) is provided, or a potential barrier is provided around the drain region. In such a configuration, by controlling the voltage of the periphery of the drain region 34 connected to a reflection electrode 30 to be in a floating state, photo carriers generated in the semiconductor substrate are caused to be hardly guided in the drain region 34.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: August 23, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Ichikawa
  • Patent number: 7999246
    Abstract: A semiconductor memory device includes a first resistance change element having a first portion and a second portion, the first portion and the second portion having a first space in a first direction, and a second resistance change element formed to have a distance to the first resistance change element in the first direction, and having a third portion and a fourth portion, the third portion and the fourth portion having a second space in the first direction, and the first space and the second space being shorter than the distance.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayoshi Iwayama
  • Patent number: 7985978
    Abstract: A display panel is disclosed. The display panel includes a data line, a scan line, a first switch connected to a first voltage, a second switch connected to a second voltage, and a pixel.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: July 26, 2011
    Assignee: Himax Technologies Limited
    Inventor: Yu-Wen Chiou
  • Patent number: 7968397
    Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Kaneko, Seiji Inumiya, Katsuyuki Sekine, Kazuhiro Eguchi, Motoyuki Sato
  • Patent number: 7960795
    Abstract: Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Renee Tong Mo, Jeffrey W. Sleight
  • Patent number: 7944033
    Abstract: An apparatus includes a housing with a plurality of restraining elements and at least one supporting element. A cover is elastically deformed by the plurality of restraining elements and the at least one supporting means. At least one substrate carrying at least one semiconductor chip is provided within the housing.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: May 17, 2011
    Assignee: Infineon Technologies AG
    Inventors: Benedikt Specht, Gottfried Ferber
  • Patent number: 7928457
    Abstract: To provide novel semiconductor light-emitting device member superior in transparency, light resistance, and heat resistance and capable of sealing semiconductor light-emitting device and holding phosphor without generating cracks or peelings even after use for a long time, the member meets the following requirements: (1) comprising functional group forming hydrogen bond with hydroxyl group or oxygen in a metalloxane bond, on the surface of ceramic or metal, (2) maintenance rate of transmittance at 400 nm wavelength before and after left at 200° C. for 500 hours is between 80% to 110%, (3) no change is observed by visual inspection after irradiated with light having 380 nm to 500 nm wavelength, whose center wavelength is between 400 nm and 450 nm both inclusive, for 24 hours with 4500 W/m2 illumination intensity at 436 nm wavelength, and (4) refractive index at 550 nm wavelength is 1.45 or larger.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 19, 2011
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Hanako Kato, Yutaka Mori, Hiroshi Kobayashi, Tsubasa Tomura, Masanori Yamazaki, Mari Abe
  • Patent number: 7923778
    Abstract: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: April 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji Yamaguchi, Atsuo Isobe, Satoru Saito
  • Patent number: 7919812
    Abstract: Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Wilfried Haensch, Amlan Majumdar
  • Patent number: 7915665
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: March 29, 2011
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • Patent number: 7915062
    Abstract: A TFT array substrate includes a TFT having an ohmic contact film and a source electrode and a drain electrode formed on the ohmic contact film. It also includes a pixel electrode electrically connected with the drain electrode. The source electrode and the drain electrode are made of an Al alloy containing Ni as an additive.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 29, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinichi Yano, Tadaki Nakahori, Nobuaki Ishiga