Patents Examined by Steven H. Rao
  • Patent number: 7786553
    Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: August 31, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 7786536
    Abstract: In a semiconductor device, a first p-type MIS transistor includes: a first gate insulating film formed on a first active region; a first gate electrode formed on the first gate insulating film; a first side-wall insulating film; a first p-type source/drain region; a first contact liner film formed over the first active region; a first interlayer insulating film formed on the first contact liner film; and a first contact plug formed to reach the top surface of the first source/drain region. The first contact liner film has a slit extending, around a corner at which the side surface of the first side-wall insulating film intersects the top surface of the first active region, from the top surface of the first contact liner film toward the corner.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: August 31, 2010
    Assignee: Panasonic Corporation
    Inventor: Shinji Takeoka
  • Patent number: 7785952
    Abstract: Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Renee Tong Mo, Jeffrey W. Sleight
  • Patent number: 7786489
    Abstract: The present invention provides a nitride semiconductor light emitting device, which comprises positive and negative electrodes with high adhesion, can output high power, and does not generate heat; specifically, the present invention provides a nitride semiconductor light emitting device comprising at least an ohmic contact layer, a p-type nitride semiconductor layer, a nitride semiconductor light emitting layer, and an n-type nitride semiconductor layer, which are laminated on a plate layer, wherein a plate adhesion layer is formed between the ohmic contact layer and the plate layer, and the plate adhesion layer is made of an alloy comprising 50% by mass or greater of a same component as a main component of an alloy contained in the plate layer.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: August 31, 2010
    Assignee: Showa Denko K.K.
    Inventors: Hiroshi Osawa, Takashi Hodota
  • Patent number: 7776307
    Abstract: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: August 17, 2010
    Assignee: Etamota Corporation
    Inventor: Thomas W. Tombler
  • Patent number: 7772635
    Abstract: A non-volatile memory device has improved performance from a stressed, silicon nitride capping layer. The device is comprised of memory cells in a substrate that have source and drain regions. A tunnel dielectric is formed over the substrate between each pair of source and drain regions. If the memory device is an NROM, a nitride charge storage layer is formed over the tunnel dielectric. If the memory device is a flash memory, a floating gate is formed over the tunnel dielectric. An inter-gate insulator and control gate are then formed over the charge storage layer. The stressed, silicon nitride capping layer is formed over the control gate.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: August 10, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Alan R. Reinberg
  • Patent number: 7772692
    Abstract: A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonao Takamatsu, Hideo Aoki, Kazunari Ishimaru
  • Patent number: 7767469
    Abstract: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Hiroaki Yoda
  • Patent number: 7767500
    Abstract: An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: August 3, 2010
    Assignee: Siliconix Technology C. V.
    Inventor: Srikant Sridevan
  • Patent number: 7768057
    Abstract: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakamura, Kenichi Imamiya
  • Patent number: 7759748
    Abstract: A semiconductor device is disclosed that comprises a fully silicided electrode formed of an alloy of a semiconductor material and a metal, a workfunction modulating element for modulating a workfunction of the alloy, and a dielectric in contact with the fully silicided electrode. At least a part of the dielectric which is in direct contact with the fully silicided electrode comprises a stopping material for substantially preventing the workfunction modulating element from implantation into and/or diffusing towards the dielectric. A method for forming such a semiconductor device is also disclosed.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: July 20, 2010
    Assignees: IMEC, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC)
    Inventors: HongYu Yu, Shou-Zen Chang, Jorge Adrian Kittl, Anne Lauwers, Anabela Veloso
  • Patent number: 7759230
    Abstract: An arrangement, process and mask for implementing single-scan continuous motion sequential lateral solidification of a thin film provided on a sample such that artifacts formed at the edges of the beamlets irradiating the thin film are significantly reduced. According to this invention, the edge areas of the previously irradiated and resolidified areas which likely have artifacts provided therein are overlapped by the subsequent beamlets. In this manner, the edge areas of the previously resolidified irradiated areas and artifacts therein are completely melted throughout their thickness. At least the subsequent beamlets are shaped such that the grains of the previously irradiated and resolidified areas which border the edge areas melted by the subsequent beamlets grow into these resolidifying edges areas so as to substantially reduce or eliminate the artifacts.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: July 20, 2010
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 7755095
    Abstract: In an LED array chip (2), LEDs (6) are connected together in series by a bridging wire (30) The LEDs (6) each have a semiconductor multilayer structure (8-18) including a light emitting layer (14) Here, the semiconductor multilayer structure (8-18) is epitaxially grown on a front surface of an SiC substrate (4) A phosphor film (48) covers the LEDs (6) Two power supply terminals (36 and 38), which are electrically independent from each other, are formed on a back surface of the SiC substrate (4) The power supply terminal (36) is connected to a cathode electrode (32) of an LED (6a) at a lower potential end by a bridging wire (40) and a plated-through hole (42) The power supply terminal (38) is connected to an anode electrode (34) of an LED (6d) at a higher potential end by a bridging wire (44) and a plated-through hole (46).
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: July 13, 2010
    Assignee: Panasonic Corporation
    Inventor: Hideo Nagai
  • Patent number: 7750406
    Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
  • Patent number: 7737538
    Abstract: A semiconductor package. The semiconductor package of the invention comprises: a substrate comprising at least one exposed area with photosensitive devices; a cover for isolating the exposed area from the external atmosphere, wherein one of either the substrate or the cover is a base, and the other is a top structure; and a dam formed on the base to form a cavity, wherein the top of the dam has a recess, the dam is attached the top structure by an adhesive, and the cavity corresponds to the exposed area.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: June 15, 2010
    Assignee: VisEra Technologies Company Limited
    Inventors: Chao-Chen Chen, Lin-Gi Yang, Chia-Chi Chou, Shih-Chieh Teng
  • Patent number: 7737437
    Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: June 15, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Hiroko Yamazaki, Atsushi Tokuda, Tetsuo Tsutsui
  • Patent number: 7732823
    Abstract: In order to make it possible to grow up a light emitting device easily on a substrate made of a Si material system while production of an anti-phase domain can be prevented and a sufficiently high luminous efficiency can be obtained, the light emitting device is configured as a device which includes a substrate (1) formed from a Si material system, a Si1-x-yGexCy (0<x?1, 0?y?0.005) layer (2) and quantum dots (3) made of a direct transition type compound semiconductor. The quantum dots (3) are included in the Si1-x-yGexCy (0<x?1, 0?y?0.005) layer (2) formed on the substrate (1).
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: June 8, 2010
    Assignee: Fujitsu Limited
    Inventor: Kenichi Kawaguchi
  • Patent number: 7732290
    Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: June 8, 2010
    Assignee: Etamota Corporation
    Inventors: Thomas W. Tombler, Jr., Brian Y. Lim
  • Patent number: 7732848
    Abstract: A semiconductor device is disclosed that improves heat dissipation by providing blind contact elements on a dielectric layer. Embodiments are disclosed which include a substrate having at least one electrode contact area accessible at a surface of the substrate and a surface adjacent the electrode contact area, a dielectric layer disposed above the surface; an intermediate oxide layer disposed above the dielectric layer, a current conducting metallization layer disposed above the intermediate oxide layer; and at least one contact element vertically extending from the dielectric layer through the intermediate oxide layer to the metallization layer above the surface adjacent the electrode contact area, the at least one contact element having a heat conductivity that is higher than that of the intermediate oxide layer.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: June 8, 2010
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Patent number: 7723786
    Abstract: A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: May 25, 2010
    Inventors: Ronald Kakoschke, Klaus Schruefer