Patents Examined by Steven H. Rao
  • Patent number: 7910962
    Abstract: To enable driving at a high withstand voltage and a large current, increase latchup immunity, and reduce ON resistance per unit area in an IGBT, a trench constituted by an upper stage trench and a lower stage trench is formed over an entire wafer surface between an n+ emitter region and a p+ collector region, and the trench is filled with a trench-filling insulating film. Thus, a drift region for supporting the withstand voltage is folded in the depth direction of the wafer, thereby lengthening the effective drift length. An emitter-side field plate is buried in the trench-filling insulating film to block a lateral electric field generated on the emitter side of the trench-filling insulating film, and as a result, an electric field generated at a PN junction between an n? drift region and a p base region is reduced.
    Type: Grant
    Filed: April 13, 2008
    Date of Patent: March 22, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Hong-fei Lu
  • Patent number: 7880185
    Abstract: In an LED array chip (2), LEDs (6) are connected together in series by a bridging wire (30). The LEDs (6) each have a semiconductor multilayer structure (8-18) including a light emitting layer (14). Here, the semiconductor multilayer structure (8-18) is epitaxially grown on a front surface of an SiC substrate (4). A phosphor film (48) covers the LEDs (6). Two power supply terminals (36 and 38), which are electrically independent from each other, are formed on a back surface of the SiC substrate (4). The power supply terminal (36) is connected to a cathode electrode (32) of an LED (6a) at a lower potential end by a bridging wire (40) and a plated-through hole (42). The power supply terminal (38) is connected to an anode electrode (34) of an LED (6d) at a higher potential end by a bridging wire (44) and a plated-through hole (46).
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: February 1, 2011
    Assignee: Panasonic Corporation
    Inventor: Hideo Nagai
  • Patent number: 7852430
    Abstract: Light guide spacers for backlighting a reflective display. Embodiments of the present invention are directed to a reflective display assembly for an electronic device which is disposed above a backlight device. A light guide extends through the reflective display to conduct light from the backlight device, through the reflective display, and to a top surface of the reflective display. The display assembly may be used with a handheld computer system.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: December 14, 2010
    Assignee: Palm, Inc.
    Inventor: Shawn R. Gettmey
  • Patent number: 7847349
    Abstract: In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and data path elements that relieve memory bandwidth limitations by pairing operands consumed by and results generated by two adjacent butterflies in the overall N-point FFT operation.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Agere Systems Inc.
    Inventor: Matthew R. Henry
  • Patent number: 7843014
    Abstract: In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: November 30, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuji Fukui, Kazuhiko Yoshino, Satoshi Hikida, Shuhji Enomoto
  • Patent number: 7838422
    Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ha Lee, Hion-suck Baik, Kwang-soo Seol, Sang-jin Park, Jong-bong Park, Min-ho Yang
  • Patent number: 7832884
    Abstract: A backlight assembly having an improved heat releasing structure and a display device having the backlight assembly are provided. The backlight assembly includes a plurality of lamps emitting light and a fixing member receiving the plurality of lamps. A separating member protruding from an edge of the fixing member defines an inner space that contains the light-lamp portions in the fixing member, and the separating member separates electrodes of the lamps from the inner space. The separating member has openings that are positioned to direct the heat generated by the lamp electrodes away from the inner space where the excess heat can cause display quality deterioration.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Han Ryu
  • Patent number: 7824996
    Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: November 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
  • Patent number: 7824976
    Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Kaneko, Kazuhiro Eguchi, Seiji Inumiya, Katsuyuki Sekine, Motoyuki Sato
  • Patent number: 7825477
    Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: November 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Shang Hsiao, Min Cao, Chung-Te Lin, Ta-Ming Kuan, Cheng-Tung Hsu
  • Patent number: 7821043
    Abstract: An insulated gate bipolar transistor has a p-type emitter layer; an n-type buffer layer provided on the p-type emitter layer; an n-type base layer provided on the n-type buffer layer and having a higher resistivity than the n-type buffer layer; a p-type base layer provided in part of an upper surface of the n-type base layer; an n-type source layer provided in part of an upper surface of the p-type base layer; a trench extending through the n-type source layer and the p-type base layer to the n-type base layer; a gate electrode provided in the trench; and a gate insulating film provided between the gate electrode and an inner surface of the trench. The p-type emitter layer has a thickness of 5 to 50 ?m and a dopant concentration of 2×1016 to 1×1018 cm?3.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akio Nakagawa
  • Patent number: 7810740
    Abstract: A plurality of the recessed portions are formed in an array on the opposite surface side of the semiconductor substrate and a second conductive type semiconductor region composed of a second conductive type semiconductor is formed at bottoms of a plurality of the recessed portions to obtain photodiode arrays arranged in an array.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: October 12, 2010
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Katsumi Shibayama, Masayuki Ishida, Takafumi Yokino
  • Patent number: 7812375
    Abstract: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Tea-Kwang Yu, Jong-Sun Sel, Ju-Hyung Kim, Byeong-In Choe
  • Patent number: 7808105
    Abstract: A semiconductor package includes a first semiconductor die; a first redistribution layer coupled to a bonding pad of the first semiconductor die; a first solder bump coupled to the first redistribution layer; a second semiconductor die; a second redistribution layer coupled to a bonding pad of the second semiconductor die; a second solder bump coupled to the second redistribution layer and to the first solder bump; a third redistribution layer coupled to the second redistribution layer; and a solder ball coupled to the third redistribution layer.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: October 5, 2010
    Assignee: Amkor Technology, Inc.
    Inventor: Jong Sik Paek
  • Patent number: 7808039
    Abstract: A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Jeffrey B. Johnson, Tak H. Ning, Robert R. Robison
  • Patent number: 7803683
    Abstract: A semiconductor device includes an insulating film formed above an upper surface of a semiconductor substrate and including a contact hole, the contact hole including an upper portion and a lower portion located on the upper portion via a boundary as a first lower end of the upper portion and a first upper end of the lower portion, the boundary including a second inner width same as the first inner width, the lower portion including a second lower end having a third inner width narrower than the second inner width, a first conductive plug made from polycrystalline silicon and formed in the lower portion of the contact hole so that the exposed upper surface of the substrate is in contact with the first conductive plug, and a second conductive plug formed on the first conductive plug and made from a conductive material different from the polycrystalline silicon.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takaharu Nishimura
  • Patent number: 7800150
    Abstract: A semiconductor is provided. The semiconductor device includes a transistor, a first strain layer and a second strain layer on a substrate. The first strain layer is configured at the periphery of the transistor. The second strain layer covers the transistor and a region exposed by the first strain layer. The stress provided by the second strain layer is different from that by the first strain layer.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: September 21, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Sheng Yang
  • Patent number: 7800158
    Abstract: There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Sung-Taeg Kang
  • Patent number: 7795711
    Abstract: An apparatus and associated method to provide localized cooling to a microelectronic device are generally described. In this regard, according to one example embodiment, a cooling apparatus comprising a heat spreader and one or more thermoelectric cooler(s) thermally coupled to the heat spreader provides cooling to one or more hot spot(s) of a microelectronic device, the one or more thermoelectric cooler(s) having a single heat exchanging element of a single material.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Ioan Sauciuc, Gregory M. Chrysler
  • Patent number: 7795624
    Abstract: A semiconductor device comprises a semiconductor element and a support body made of a stack of ceramic layers having a recess in which electrical conductors are electrically connected with the semiconductor element, wherein at least a part of a top face of a recess side wall is covered by a resin, thereby providing a light emitting device.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: September 14, 2010
    Assignee: Nichia Corporation
    Inventor: Kensho Sakano