Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above an upper surface of the substrate and including a contact hole penetrating the insulating film, a wiring portion formed on the insulating film, and a contact plug formed in the contact hole and including a first conductive plug formed in a lower portion of the contact hole so that the exposed upper surface of the semiconductor substrate is in contact with the first conductive plug and a second conductive plug formed on the first conductive plug, so that the wiring portion is in contact with the second conductive plug. The first and second conductive plugs have an interface with a height that is lower than a height of the boundary portion relative to an upper surface of the semiconductor substrate.

Abstract: A design structure comprising an apparatus which reduces the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring sense amplifier assist (SAA) circuitry. The design structure limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.

Abstract: The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin layer. The gold plating layer is formed in an wiring layer area for the pad electrode. The surface outside the area is roughened. The insulating resin layer is formed so as to cover the wiring layer and to have an opening in an area in which the pad electrode is formed. The circuit element is mounted on a predetermined area on the insulating resin layer. The sealing resin layer is formed on the insulating resin layer so as to entirely cover the circuit element and the opening for the pad electrode. The sealing resin layer, in the area for the pad electrode, is in contact with the gold plating layer and the wiring layer.

Abstract: A transistor that forms an integrated circuit, a photo detector and a micromirror are mounted on the same semiconductor substrate in an optical semiconductor device of the present invention, which has an antireflection film that is formed on the photo detector, a first insulating film which is formed on the antireflection film and in which an opening is created in the state where the antireflection film is exposed, and an etching stopping film which is formed on the first insulating film and which has been left in the periphery around the opening in the first insulating film on the antireflection film and in the periphery around the portion above the micromirror.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

Abstract: A semiconductor light emitting apparatus comprises: a semiconductor light emitting device; resin that seals the semiconductor light emitting device; and antireflective coating provided on a surface of the resin. The antireflective coating is made of material having an intermediate refractive index between the refractive index of the resin and the refractive index of air.

Abstract: The present invention provides a constitution of n-type ohmic electrode suitable for n-type group III nitride semiconductor, and a forming method thereof for providing low contact resistivity. The n-type ohmic electrode is provided to comprise an alloy of aluminum and lanthanum or comprises lanthanum at the junction interface with the n-type group III nitride semiconductor. The method comprising forming a lanthanum-aluminum alloy layer at 300° C. or less to form an n-type ohmic electrode enriched in lanthanum at the junction interface.

Abstract: There are provided an organic light-emitting device having a light output of a high emission efficiency and a high luminance and having high durability and a novel organic compound that enables the device to be attained. An organic compound of a long fluorescence lifetime represented by an organic compound having, in a molecule, at least one partial structure comprising an unsubstituted or substituted indole ring and at least one partial structure comprising an unsubstituted or substituted carbazole ring is used in an organic light-emitting device.

Abstract: A photodetector and a method for fabricating a photodetector. The photodetector may include a substrate, a buffer layer formed on the substrate, and an absorption layer formed on the buffer layer for receiving incident photons and generating charged carriers. An N-doped interface layer may be formed on the absorption layer, an N-doped cap layer may be formed on the N-doped interface layer, and a dielectric passivation layer may be formed above the cap layer. A P+ diffusion region may be formed within the cap layer, the N-doped interface layer and at least a portion of the absorption layer, and at least one contact may be formed on and coupled to the P+ diffusion region.

Abstract: A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x?0.25, y?0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH3GeH3 species was prepared using a new and high yield method that provided high purity semiconductor grade material.

Abstract: A semiconductor device has transistors (P1,P10,P11) formed in an active region (22) isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P10,P11) that require symmetry or relativity characteristics, wherein the distances (S1) between a gate electrode and one end of the active region on a source side viewed from the gate electrode in the first and second transistor are substantially same, and the distances (D1) between a gate electrode and one end of the active region on a drain side viewed from the gate electrode in the first and second transistor are substantially same. The predetermined circuit includes, for example, a current mirror circuit that has a transistor pair of which gate is commonly connected, and a differential circuit that has a transistor pair whose sources are commonly connected, where an input signal is supplied to the gate, and an output signal is generated in the drain.

Abstract: Provided is a wafer-scale microcolumn array using a low temperature co-fired ceramic (LTCC) substrate. The microcolumn array includes a LTCC substrate having wirings and wafer-scale beam deflector arrays, which are attached to at least one side of the LTCC substrate and has an array of deflection devices deflecting electron beams. The wafer-scale microcolumn array using the LTCC substrate makes it possible to significantly increase the throughput of semiconductor wafers, simplify its manufacturing process, and lower its production cost.

Abstract: A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Connected to and extending between the outer frame portion and the peripheral edge of the die pad is at least one tie bar of the leadframe. The leadframe also includes a plurality of leads which are connected to the outer frame portion and extend into the opening at least partially about the die pad in spaced relation to the peripheral edge thereof. Each of the leads includes opposed, generally planar top and bottom lead surfaces, with at least two of the leads comprising corner leads which extend along opposed sides of the tie bar. Each of the corner leads further defines an angularly offset distal portion which extends along and in spaced relation to the tie bar.

Abstract: A method for releasing from underlying substrate material micromachined structures or devices without application of chemically aggressive substances or excessive forces. The method starts with the step of providing a partially formed device, comprising a substrate layer, a sacrificial layer deposited on the substrate, and a function layer deposited on the sacrificial layer and possibly exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Next there are the steps of cleaning residues from the surface of the device, and then directing high-temperature hydrogen gas over the exposed surfaces of the sacrificial layer to convert the silicon dioxide to a gas, which is carried away from the device by the hydrogen gas.

Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a metal compound film directly or indirectly on a semiconductor substrate, forming a metal-containing insulating film consisting of a metal oxide film or a metal silicate film by oxidizing the metal compound film, and forming an electrode on the metal-containing insulating film.