Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

Abstract: A packaged sensor assembly and method of forming that includes a first substrate having opposing first and second surfaces and a plurality of conductive elements each extending between the first and second surfaces. A second substrate comprises opposing front and back surfaces, one or more detectors formed on or in the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the one or more detectors. A third substrate is mounted to the front surface to define a cavity between the third substrate and the front surface, wherein the third substrate includes a first opening extending from the cavity through the third substrate. The back surface is mounted to the first surface. A plurality of wires each extend between and electrically connecting one of the contact pads and one of the conductive elements.

Abstract: A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.

Abstract: A method includes providing a structure having a substrate, a first insulating layer on the substrate, a first semiconductor material layer on the first insulating layer, a second insulating layer on the first semiconductor layer in a first portion of the structure and a second semiconductor layer of a second, different semiconductor material on the second insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure forming a regrown semiconductor layer; forming first fins in the regrown semiconductor layer and second fins in the second semiconductor layer; and forming gate structures upon the first and second fins. A height difference, relative to a surface of the first insulating layer, of the gate structures formed upon the first fins and the gate structures formed upon the second fins is less than a predetermined value.

Abstract: A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.

Abstract: A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed.

Abstract: An electronic device comprising: an electronic substrate comprising circuit elements; a double bank well-defining structure disposed over the electronic substrate, the double bank well-defining structure comprising a first layer of insulating material and a second layer of insulating material thereover, the second layer of insulating material having a lower wettability than the first layer of insulating material; and organic semiconductive material disposed in wells defined by the double bank well-defining structure.

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract: Methods of fabricating patterned substrates, including patterned graphene substrates, using etch masks formed from self-assembled block copolymer films are provided. Some embodiments of the methods are based on block copolymer (BCP) lithography in combination with graphoepitaxy. Some embodiments of the methods are based on BCP lithography techniques that utilize hybrid organic/inorganic etch masks derived from BCP templates. Also provided are field effect transistors incorporating graphene nanoribbon arrays as the conducting channel and methods for fabricating such transistors.

Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

Abstract: The present disclosure involves an illumination apparatus. The illumination apparatus includes an n-doped semiconductor compound layer, a p-doped semiconductor compound layer spaced apart from the n-doped semiconductor compound layer, and a multiple-quantum-well (MQW) disposed between the first semiconductor compound layer and the second semiconductor compound layer. The MQW includes a plurality of alternating first and second layers. The first layers of the MQW have substantially uniform thicknesses. The second layers have graded thicknesses with respect to distances from the p-doped semiconductor compound layer. A subset of the second layers located most adjacent to the p-doped semiconductor compound layer is doped with a p-type dopant. The doped second layers have graded doping concentration levels that vary with respect to distances from the p-doped semiconductor layer.

Abstract: A transistor including an oxide semiconductor with favorable electric characteristics and a manufacturing method thereof are provided. A semiconductor device includes a transistor. The transistor includes an oxide semiconductor film over a base insulating film, a gate electrode overlapping with the oxide semiconductor film with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film and serving as a source electrode and a drain electrode. The base insulating film includes a first oxide insulating film partly in contact with the oxide semiconductor film and a second oxide insulating film in the periphery of the first oxide insulating film. An end portion of the oxide semiconductor film which crosses the channel width direction of the transistor is located over the first oxide insulating film.

Abstract: A shielded junction field effect transistor (JFET) is described having gate trenches and shield trenches, the shield trenches being deeper and narrower than the gate trenches. The gate trenches may be fully aligned, partially aligned, or separated from the shield trenches.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

Abstract: A semiconductor device includes a first-conductive type first pillar, a first dielectric surrounding the first pillar, a gate surrounding the dielectric, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface with the first pillar, and a first-conductive type region surrounded by the second-conductive type region. The third pillar has a second-conductive type impurity region in a surface thereof except a part of a contact surface with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region of the third pillar. The first-conductive type region of each of the second and third pillars has a length greater than that of a depletion layer extending from a base of the second-conductive type region of one of the second and third pillars.

Abstract: Frontside-illuminated barrier infrared photodetector devices and methods of fabrication are disclosed. In one embodiment, a frontside-illuminated barrier infrared photodetector includes a transparent carrier substrate, and a plurality of pixels. Each pixel of the plurality of pixels includes an absorber layer, a barrier layer on the absorber layer, a collector layer on the barrier layer, and a backside electrical contact coupled to the absorber layer. Each pixel has a frontside and a backside. The absorber layer and the barrier layer are non-continuous across the plurality of pixels, and the barrier layer of each pixel is closer to a scene than the absorber layer of each pixel. A plurality of frontside common electrical contacts is coupled to the frontside of the plurality of pixels, wherein the frontside of the plurality of pixels and the plurality of frontside common electrical contacts are bonded to the transparent carrier substrate.

Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.

Abstract: An LED device includes a strip-shaped electrode, a strip-shaped current blocking structure and a plurality of distributed current blocking structures. The current blocking structures are formed of an insulating material such as silicon dioxide. The strip-shaped current blocking structure is located directly underneath the strip-shaped electrode. The plurality of current blocking structures may be disc shaped portions disposed in rows adjacent the strip-shaped current blocking structure. Distribution of the current blocking structures is such that current is prevented from concentrating in regions immediately adjacent the electrode, thereby facilitating uniform current flow into the active layer and facilitating uniform light generation in areas not underneath the electrode. In another aspect, current blocking structures are created by damaging regions of a p-GaN layer to form resistive regions.