Abstract: Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.

Abstract: Disclosed is a light-emitting element comprising a plurality of light-emitting units which are separated from one another by a charge generation layer. The light-emitting units each have a light-emitting layer which is featured by a stack of two layers. Each of the two layers includes a host material and a phosphorescent material where the phosphorescent material in one of the two layers is blue emissive while the phosphorescent material in the other of the two layers exhibits a maximum emission peak in a range from 500 nm to 700 nm. The phosphorescent material exhibiting a maximum emission peak in a range from 500 nm to 700 nm may be different from light-emitting unit to light-emitting unit. An additive may be included in at least one of the two layers so that an exciplex is formed with the host material.

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Abstract: A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device.

Abstract: Embodiments of the invention describe substrates, used to form optical devices, which include high thermal conductivity intermediate layers. Said substrates comprise a bulk layer, an optical device layer comprising a first material, and an intermediate layer disposed between the bulk layer and the device layer comprising a second material having a higher thermal conductivity and a lower index of refraction than the first material. In the resulting devices, said intermediate layer functions as part of the device layer structure—i.e., provides optical or electrical power dissipation (i.e. thermal) functionality for the device formed from said substrate. Thus, optical devices do not necessarily need to utilize an add-on packaging solution for heat absorption when formed from substrate stacks according to embodiments of the invention.

Abstract: A semiconductor device includes an active region including a surface region and a first recess formed on both sides of the surface region, the active region extending along a first direction; a device isolation structure surrounding the active region; a pair of gate lines extending along the surface region of the active region in a second direction perpendicular to the first direction; a plurality of second recesses formed in the device isolation structure beneath the gate lines and including given portions of the gate lines filled into the second recesses; a plurality of first junction regions formed in the active region beneath the first recesses; and a second junction region formed in the surface region between the gate lines, wherein the second junction region defines at least two vertical-type channels below the gate line with the plurality of first junction regions.

Abstract: An electromechanical transducer includes multiple elements each including at least one cellular structure, the cellular structure including: a semiconductor substrate, a semiconductor diaphragm, and a supporting portion for supporting the diaphragm so that a gap is formed between one surface of the substrate and the diaphragm. The elements are separated from one another at separating locations of a semiconductor film including the diaphragm. Each of the elements includes in a through hole passing through a first insulating layer including the supporting portion and the semiconductor substrate: a conductor which is connected to the semiconductor film including the diaphragm; and a second insulating layer for insulating the conductor from the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

Abstract: Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner. Conductors, joined to electrically isolating materials, are exposed to electrical fields in such a manner as to form one or more anodes to corresponding cathodes, thus liberating metal ions. The metal ions are then allowed to migrate in a controlled manner from the anode toward the cathode to form a pre-migrated metal. Finally, an inhibitor is applied on top of the pre-migrated metal to prevent further migration.

Abstract: A capacitive pressure sensor includes: a semiconductor substrate having a reference pressure chamber formed therein; a diaphragm which is formed in a front surface of the semiconductor substrate and has a ring-like peripheral through hole penetrating between the front surface of the semiconductor substrate and the reference pressure chamber and defining an upper electrode and a plurality of central through holes; a peripheral insulating layer which fills the peripheral through hole and electrically isolates the upper electrode from other portions of the semiconductor substrate; and a central insulating layer which fills the central through holes.

Abstract: Embodiments of the present disclosure are directed to laser removal of resist material from integrated circuit (IC) packaging components, as well as package assemblies and systems incorporating such material and removal methods. A resist layer may be applied to one or more components of a package assembly. The resist layer may be subsequently removed by applying laser radiation and a flow of fluid to the resist layer. The laser radiation may cause cracking, delamination, and/or polymer chain scission, and the flow of fluid may enhance mechanical separation of the resist material from the package assembly components.

Abstract: A semiconductor device and manufacture method thereof include a silicide material formed on a source region and a drain region on opposite sides of a gate, wherein the gate having sidewalls on both side surfaces is formed on a substrate. The gate has a first sidewall spacer and a second sidewall spacer on each sidewall, the first spacer has a horizontal portion and a vertical portion, the horizontal portion is located between the second sidewall spacer and the substrate, the vertical portion is located between the second sidewall spacer and the sidewalls. A protecting layer is selectively deposited on the silicide material.

Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

Abstract: An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.

Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

Abstract: A graphene based detector device can include a source, a drain, and a gate. The gate can incorporate a discharging element and a graphene sheet that is proximate to the discharging element. The graphene sheet for the transistor can have a decreasing width, from a maximum width w2 distal to the discharging element to a minimum width w1 proximate to the discharging element. An electric potential can be established across graphene sheet, to facilitate funneling of the electrons from the graphene sheet (which are caused by quanta of electromagnetic radiation) toward the discharging element. The devices can be formed in an array to establish an antenna that operates according to the quantum nature of light, as opposed to resonance (wavelength). Multiple graphene layers that are doped using different materials can be included. The multiple layer funnel electrons at specific frequencies, to create an operating frequency range for the device.

Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.

Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Abstract: Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.

Abstract: Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the resulting devices, are disclosed. Embodiments include: providing, on a substrate, a RX pad having a SPM with a SPM horizontal and vertical positions at horizontal and vertical midpoints, respectively, of the first RX pad; providing a second RX pad abutting the first RX pad and a first STI pad abutting the second RX pad, each having a vertical midpoint at the SPM vertical position; forming a first gate alignment mark on the second RX pad and having vertical endpoints horizontally aligned with vertical endpoints of the second RX pad; and forming a second gate alignment mark on the first STI pad and having vertical endpoints horizontally aligned with vertical endpoints of the first STI pad.