Abstract: A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.

Abstract: Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another.

Abstract: A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.

Abstract: A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

Abstract: Techniques for quantifying ?Dfin in FINFET technology are provided. In one aspect, a method for quantifying ?Dfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ?Vth for the pair of long channel FINFET devices; and (c) using the ?Vth to determine the ?Dfin between the pair of long channel FINFET devices, wherein the ?Vth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ?Vth is proportional to the ?Dfin between the pair of long channel FINFET devices.

Abstract: A semiconductor package includes a semiconductor wafer having a plurality of semiconductor die. A contact pad is formed over and electrically connected to an active surface of the semiconductor die. A gap is formed between the semiconductor die. An insulating material is deposited in the gap between the semiconductor die. An adhesive layer is formed over a surface of the semiconductor die and the insulating material. A via is formed in the insulating material and the adhesive layer. A conductive material is deposited in the via to form a through hole via (THV). A conductive layer is formed over the contact pad and the THV to electrically connect the contact pad and the THV. The plurality of semiconductor die is singulated. The insulating material can include an organic material. The active surface of the semiconductor die can include an optical device.

Abstract: An SOI substrate including a semiconductor layer whose thickness is even is provided. According to a method for manufacturing the SOI substrate, the semiconductor layer is formed over a base substrate. In the method, a first surface of a semiconductor substrate is polished to be planarized; a second surface of the semiconductor substrate which is opposite to the first surface is irradiated with ions, so that an embrittled region is formed in the semiconductor substrate; the second surface is attached to the base substrate, so that the semiconductor substrate is attached to the base substrate; and separation in the embrittled region is performed. The value of 3? (? denotes a standard deviation of thickness of the semiconductor layer) is less than or equal to 1.5 nm.

Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.

Abstract: A display device includes a pixel area including pixels arranged in a matrix and having a horizontal resolution of 350 ppi or more and a color filter layer overlapping with the pixel area. The pixels each include a first transistor whose gate is electrically connected to a scan line and whose one of a source and a drain is electrically connected to a signal line; a second transistor whose gate is electrically connected to the other of the source and the drain of the first transistor and whose one of a source and a drain is electrically connected to a current-supplying line; and a light-emitting element electrically connected to the other of the source and the drain of the second transistor. The first and second transistors each have a channel formation region including a single crystal semiconductor.

Abstract: To improve light extraction efficiency of light emitting elements such as electroluminescent elements. A first electrode 101, a light emitting layer 102, and a second electrode 103 are formed over a substrate 100, which partially constitute a light emitting element. Light produced in the light emitting layer 102 is emitted out through the second electrode 103. A plurality of three-dimensional bodies 104 are provided in contact with a surface of the second electrode 103. With the provision of the bodies 104, light totally reflected between the second electrode 103 and the air enters the bodies 104 and can be emitted through faces of the bodies 104 that are not parallel to the interface between the bodies and the second electrode 103.

Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. In a transistor using an oxide semiconductor film for an active layer, a microvoid is provided in a source region and a drain region adjacent to a channel region. By providing a microvoid in the source region and the drain region formed in an oxide semiconductor film, hydrogen contained in the channel region of an oxide semiconductor film can be captured in the microvoid.

Abstract: According to one embodiment, a magnetic memory element includes a stacked body and a conductive shield. The stacked body includes first and second stacked units. The first stacked unit includes first and second ferromagnetic layers and a first nonmagnetic layer. The first ferromagnetic layer has a fixed magnetization in a first direction. A magnetization direction of the second ferromagnetic layer is variable in a second direction. The first nonmagnetic layer is provided between the first and second ferromagnetic layers. The second stacked unit includes a third ferromagnetic layer stacked with the first stacked unit in a stacking direction of the first stacked unit. A magnetization direction of the third ferromagnetic layer is variable in a third direction. The conductive shield is opposed to at least a part of a side surface of the second stacked unit. An electric potential of the conductive shield is controllable.

Abstract: A current-amplifying transistor device is provided, between an emitter electrode and a collector electrode, with two organic semiconductor layers and a sheet-shaped base electrode. One of the organic semiconductor layers is arranged between the emitter electrode and the base collector electrode, and has a diode structure of a p-type organic semiconductor layer and an n-type p-type organic semiconductor layer. A current-amplifying, light-emitting transistor device including the current-amplifying transistor device and an organic EL device portion formed in the current-amplifying transistor device is also disclosed.

Abstract: A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.

Abstract: A semiconductor device includes a first gate electrode; a gate insulating layer covering the first gate electrode; an oxide semiconductor layer that overlaps with the first gate electrode; oxide semiconductor layers having high carrier density covering end portions of the oxide semiconductor layer; a source electrode and a drain electrode in contact with the oxide semiconductor layers having high carrier density; an insulating layer covering the source electrode, the drain electrode, and the oxide semiconductor layer; and a second gate electrode that is in contact with the insulating layer. Each of the oxide semiconductor layers is in contact with part of each of an upper surface, a lower surface, and a side surface of one of the end portions of the oxide semiconductor layer and part of an upper surface of the gate insulating layer.

Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.

Abstract: A light-scattering substrate which can be thinned and has improved thermal resistance, a method of manufacturing the same, an organic light-emitting display device including the same, and a method of manufacturing the organic light-emitting display device are disclosed. The light-scattering substrate includes a light-scattering layer composed of a plurality of metal nanoparticles which are attached to at least a surface of a substrate. The metal nanoparticles are formed by agglomeration of a metal on the substrate, and show a surface plasmon phenomenon.

Abstract: An LED package structure comprises a 3D substrate, LED chips, wires, and resin encapsulants. The 3D substrate has a stepped contour and includes a first chip accommodation region and at least one second chip accommodation region surrounding the first chip accommodation region. A first electric contact and a second electric contact are arranged in the first chip accommodation region. The LED chips are arranged in the border of the 3D substrate. The wires are used to connect the LED chips in series or in series firstly and in parallel next. One of the wires connects the first electric contact and one of the LED chips. Another one of the wires connects the second electric contact and another one of the LED chips. The resin encapsulants respectively encapsulate the LED chips. The LED package structure is characterized in using a 3D substrate to facilitate wiring and increase the beam angle.

Abstract: A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.

Abstract: Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.