Patents Examined by Steven J. Mottola
  • Patent number: 11038476
    Abstract: The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The system includes a power amplification device capable of minimizing the effect of envelope impedance. The power amplification device may be incorporated in a terminal and a base station.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 15, 2021
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jihoon Kim, Bumman Kim, Kyunghoon Moon, Seokwon Lee, Daechul Jeong, Byungjoon Park, Juho Son
  • Patent number: 11031913
    Abstract: In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Cree, Inc.
    Inventors: Madhu Chidurala, Marvin Marbell, Simon Ward
  • Patent number: 11025213
    Abstract: A circuit includes a first transconductance stage having an output. The circuit further includes an output transconductance stage, and a first source-degenerated transistor having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aniruddha Roy, Saurabh Pandey
  • Patent number: 11025215
    Abstract: Neuromodulation systems in accordance with embodiments of the invention can use a feed-forward common-mode cancellation (CMC) path to attenuate common-mode (CM) artifacts appearing at a voltage input, thus allowing for the simultaneous recording of neural data and stimulation of neurons. In several embodiments of the invention, the feed-forward CMC path is utilized to attenuate the common-mode swings at Vin,CM, which can restore the linear operation of the front-end for differential signals. In several embodiments, the neuromodulation system may utilize an anti-alias filter (AAF) that includes a duty-cycles resistor (DCR) switching at a first frequency f1, followed by a DCR switching at a second frequency f2. The AAF allows for a significantly reduced second frequency f2 that enables the multi-rate DCR to increase the maximum realizable resistance, which is dependent upon the frequency ratio f1/f2.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: June 1, 2021
    Assignee: The Regents of the University of California
    Inventors: Hariprasad Chandrakumar, Dejan Markovic
  • Patent number: 11018629
    Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 25, 2021
    Assignee: NXP USA, Inc.
    Inventors: Seungkee Min, Margaret A. Szymanowski
  • Patent number: 11018630
    Abstract: Provided are embodiments that include a circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source. The circuit includes an operational amplifier, and a switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier. Also provided are embodiments for a method for operating a circuit in a disabled mode for error reduction.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 25, 2021
    Assignee: HAMILTON SUNSTRAND CORPORATION
    Inventors: Thomas P. Joyce, Matthew Campbell
  • Patent number: 11012037
    Abstract: This disclosure describes auto-zero amplifier circuit that include an additional capacitor (or other capacitive component) that can be switchably coupler to a reference voltage. The auto-zero amplifier circuit can generate an auto-zero compensation signal using a difference between the reference voltage stored on the additional capacitor and a voltage stored on another auto-zero capacitor.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 18, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Hai Chen, Gregory J. Hughes
  • Patent number: 11012041
    Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 18, 2021
    Assignee: ABLIC INC.
    Inventors: Hideyuki Sawai, Tsutomu Tomioka, Tadakatsu Kuroda
  • Patent number: 11012045
    Abstract: A variable gain amplifier circuit is disclosed. In one embodiment, an amplifier circuit includes first and second stages. Each stage includes one or more inverter pairs, with one inverter of each pair coupled to receive an inverting component of a differential signal and the other inverter of the pair coupled to receive a non-inverting component. The first stage receives a differential input signal and produces an intermediate differential signal. The second stage receives the intermediate differential signal and produces a differential output signal, the differential output signal being an amplified version of the differential input signal.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 18, 2021
    Assignee: Apple Inc.
    Inventors: Sang Hyun Woo, Paul-Aymeric H. Fontaine
  • Patent number: 11012046
    Abstract: In a gain control device, a gain control voltage adjust circuit includes a time-constant circuit and outputs an adjusted gain control voltage depending on an adjustment signal and a control voltage generated by a differential amplifier upon input of the adjustment signal. An adjustment signal generation circuit outputs the adjustment signal during an adjustment signal output period. This period is a specified period before a first burst signal is output from a signal output unit and where a burst signal is not output from the signal output unit. The adjustment signal is to make the adjusted gain control voltage closer to a target voltage. The target voltage is a gain control voltage output from the gain control voltage adjust circuit and corresponding to a steady part of a second burst signal. The second burst signal is a burst signal output before the first burst signal.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 18, 2021
    Assignee: JVCKENWOOD Corporation
    Inventor: Nobuyoshi Kurushima
  • Patent number: 11005429
    Abstract: A first transistor, a second transistor, a third transistor, and a fourth transistor, their source terminals being grounded, are provided. Further, a first feedback circuit connected between a gate terminal and a drain terminal in the first transistor, and having first impedance, a second feedback circuit connected between a gate terminal and a drain terminal in the second transistor, and having the first impedance, a current source for outputting a current, a first load circuit connected between the drain terminal of the first transistor and a first output terminal of the current source, and having second impedance, and a second load circuit connected between the drain terminal of the second transistor and a second output terminal of the current source, and having the second impedance are provided.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 11, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takaya Maruyama, Koji Tsutsumi
  • Patent number: 11005425
    Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: May 11, 2021
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11005424
    Abstract: A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Kathiravan Krishnamurthi, Souleymane Gnanou, Douglas S. Jansen
  • Patent number: 10998858
    Abstract: A power supply circuit comprises a power conversion circuit, a voltage selection circuit, and a voltage regulator. The voltage regulator coupled to the voltage selection circuit and a digital-to-analog converter (DAC), and the voltage regulator is configured to provide supply power to the DAC; the power conversion circuit is coupled to a first power supply and a power amplifier (PA), and the power conversion circuit is configured to convert, based on output power of the PA, a voltage of the first power supply into an output voltage that supply power to the PA; and the voltage selection circuit is coupled to a second power supply, the power conversion circuit and the voltage regulator, and the voltage selection circuit is configured to select the second power supply or the power conversion circuit to supply power to the voltage regulator based on an output voltage of the power conversion circuit.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 4, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Xun Zhang
  • Patent number: 10985702
    Abstract: An envelope tracking system is disclosed having an envelope tracking integrated circuit (ETIC) with a first tracker having a first supply output and a second tracker having a second supply output, wherein the ETIC has a first mode in which only one of the first and second trackers supplies voltage and a second mode in which the first and second trackers both supply voltage. A first notch filter is coupled to the first supply output and a second notch filter is coupled to the second supply output. A mode switch coupled between the first supply output and the second supply output is configured to couple the first notch filter and the second notch filter in parallel in the first mode and open the mode switch to decouple the first notch filter from the second notch filter in the second mode in response to first and second switch control signals, respectively.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 20, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Michael R. Kay
  • Patent number: 10985722
    Abstract: Disclosed herein are methods for amplifying a signals. The methods include receiving signals at a plurality of input nodes. The methods also include configuring a gain stage to be in a selected one of a plurality of gain settings, at least some of the gain settings resulting in different impedances presented to the signal. The methods also include adjusting the resistance presented to the signal by the gain stage for the selected gain setting, the adjusted resistance being configured to provide a targeted constant value of the impedance at the input across the plurality of gain settings. The methods also include amplifying at least a portion of the received signals. Adjusting the resistance compensates for changes to the input impedance to improve return loss and mismatch over gain modes.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 20, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Junhyung Lee
  • Patent number: 10985718
    Abstract: Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 20, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Tsutomu Murata
  • Patent number: 10985720
    Abstract: A circuit includes a first amplifier having first and second inputs and first and second output, first and second input capacitors, a first feedback capacitor selectively coupled between the first input and the first output, and a second feedback capacitor selectively coupled between the second input and the second output. During a second phase of operation, the first and second feedback capacitors are decoupled from the output and the first amplifier is configured to sample an input common mode voltage, an output common mode voltage, and an input offset voltage of the first amplifier on the first and second input capacitors. During a first phase of operation, the first feedback capacitor is coupled between the input and the output, the second feedback capacitor is coupled between the input and the output, and the first amplifier is configured to amplify a differential input signal provided across the first and second inputs.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 20, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Martin Drinovsky, Karel Znojemsky
  • Patent number: 10985710
    Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: April 20, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shota Ishihara, Yuji Shintomi, Satoshi Matsumura
  • Patent number: 10979008
    Abstract: A power amplifier includes a first amplifier configured to output a signal based on a difference between an input signal and a feedback signal; a second amplifier that amplifies the power of the signal output from the first amplifier and outputs the amplified signal; a first feedback circuit that feeds the signal output from the second amplifier back to the first amplifier; a third amplifier that amplifies the power of the signal output from the second amplifier and outputs the amplified signal; and a second feedback circuit that feeds the signal output from the third amplifier back to the first amplifier, in which the feedback signal is a signal obtained by combining an output signal of the first feedback circuit with an output signal of the second feedback circuit.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 13, 2021
    Assignee: Yamaha Corporation
    Inventor: Eiji Zen