Patents Examined by Steven J. Mottola
  • Patent number: 10727797
    Abstract: A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: George Reitsma
  • Patent number: 10727794
    Abstract: An apparatus includes an amplifier, an input port, a first modulator circuit connected to the input port, and a correction circuit. The correction circuit is configured to determine a common mode voltage of the input port and receive a first clock signal. The correction circuit is further configured to manipulate, based at least in part upon the common mode voltage of the input port, the first clock signal to generate a second clock signal. The second clock signal is produced for the first modulator circuit. The correction circuit is further configured to determine whether the second clock signal is out of phase with a third clock signal, and, based upon a determination that the second clock signal is out of phase with the third clock signal, reset the second clock signal.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 28, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Serban Motoroiu, James Nolan
  • Patent number: 10720891
    Abstract: The present invention addresses method, apparatus and computer program product for stabilization of the direct learning algorithm for wideband signals. Thereby, a signal to be amplified is input to a pre-distorter provided for compensating for non-linearity of the power amplifier, and the pre-distorted output signal from the pre-distorter is forwarded to the power amplifier. Parameters of the pre-distorter are adapted based on an error between the linearized signal output from the power amplifier and the signal to be amplified using an adaptive direct learning algorithm, and the linear system of equations formed by the direct learning algorithm are solved using a conjugate gradient algorithm, wherein, once per direct learning algorithm adaptation, at least one of the initial residual and the initial direction of the conjugate gradient algorithm are set based on the result of the previous adaptation.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 21, 2020
    Assignee: Nokia Solutions And Networks GMBH And Co. KG
    Inventors: Christian Reichl, Shavantha Kularatna, Rene Roeschke, Bjoern Jelonnek
  • Patent number: 10720937
    Abstract: A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jun Zhang
  • Patent number: 10715088
    Abstract: A low noise amplifier has integral noise cancellation to provide a low noise figure and operation over a frequency range of 0.5 GHz-50 GHz. An amplifier amplifies an input signal as well as noise present with the amplified signal and amplified noise being out of phase and in phase, respectively, with the corresponding inputs. A feedback circuit that is non-linear with frequency enables a constant amplification. A summation circuit combines amplified signals with the noise being cancelled since two combined noise signals being summed are 180 degrees out of phase to each other. An optional secondary amplification stage provides additional amplification. Preferably, the amplifier, auxiliary amplifier and the summation device utilize CMOS transistors disposed on an SOI substrate with impedance stabilization over the frequency range.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 14, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Manouchehr Ghanevati, Timothy R. LaRocca
  • Patent number: 10712304
    Abstract: This application relates to methods and apparatus for operating MEMS sensors, in particular MEMS capacitive sensors (CMEMS) such as a microphones. An amplifier apparatus is arranged to amplify an input signal (VINP) received at a sense node from the MEMS capacitive sensor. An antiphase signal generator generates a second signal (VINN) which is in antiphase with the input signal (VINP) and an amplifier arrangement is configured to receive the input signal (VINP) at a first input and the second signal (VINN) at a second input and to output corresponding amplified first and second output signals. This converts a single ended input signal effectively into a differential input signal.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 14, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Paul Wilson, Karthikeya Kodur
  • Patent number: 10700647
    Abstract: A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 30, 2020
    Assignee: MEDIATEK INC.
    Inventor: Che-Hsun Kuo
  • Patent number: 10700645
    Abstract: Power amplification system with adaptive bias control. In some embodiments a power amplification system includes a power amplifier including a radio-frequency (RF) input terminal for receiving an RF signal, an RF output terminal for providing an amplified RF signal, a supply voltage terminal for receiving a power amplifier supply voltage to power the power amplifier, and one or more bias terminals for receiving one or more bias signals. The power amplification system also includes a bias controller configured to provide the one or more bias signals to the one or more bias terminals, at least one of the one or more bias signals being based on the power amplifier supply voltage.
    Type: Grant
    Filed: July 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Matthew Lee Banowetz, Philip H. Thompson
  • Patent number: 10700652
    Abstract: Some aspects of the disclosure provide for a circuit. In an example, the circuit includes an amplifier, a first transistor network, a second transistor network, a first resistor, a second resistor, and a third resistor. The amplifier has first and second inputs and first, second, third, and fourth outputs. The first transistor network is coupled to the first output of the amplifier and the second output of the amplifier. The second transistor network is coupled to the third output of the amplifier and the fourth output of the amplifier. The first resistor is coupled between the first transistor network and the second transistor network. The second resistor is coupled between the first transistor network and the first input of the amplifier. The third resistor is coupled between the second transistor network and the second input of the amplifier.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 30, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vikram Sharma, Gokul Koraganji
  • Patent number: 10693426
    Abstract: An integrated amplifier device includes a main amplifier configured to be coupled to an input source. A replica amplifier is coupled to the main amplifier to provide a bias to the main amplifier. A transconductance biasing cell to the main amplifier and the replica amplifier. The transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier. A method of making an integrated amplifier device is also disclosed.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 23, 2020
    Assignee: INTRINSIX CORP.
    Inventor: Daniel J. Segarra
  • Patent number: 10686408
    Abstract: The present invention relates to a four-way Doherty amplifier. The invention further relates to a mobile telecommunications base station. The invention proposes a new Doherty combiner topology that allows peak efficiencies to be reached at deeper back-off levels than conventional Doherty combiners.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 16, 2020
    Assignee: Ampleon Netherlands B.V.
    Inventor: Xiaochuan Jiang
  • Patent number: 10686418
    Abstract: Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide a low gain bandwidth product to amplify at a higher speed and a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may achieve the low and high gain bandwidth product by generating a first current and a second current through a plurality of sets of series-connected transistors and operating a plurality of switches.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Tsutomu Murata
  • Patent number: 10680564
    Abstract: Aspects of this disclosure relate to an adaptive biasing circuit for a power amplifier. The adaptive biasing circuit can include a shunt resistor arrangement and/or a floating gate linearizer arrangement.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 9, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Mohamed Moussa Ramadan Esmael, Mohamed Ahmed Youssef Abdalla
  • Patent number: 10680561
    Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: June 9, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Yuji Shintomi, Satoshi Matsumura
  • Patent number: 10673389
    Abstract: Chopper amplifiers with high pass filters for suppressing chopping ripple are provided herein. In certain embodiments, a chopper amplifier includes an input chopping circuit, an amplification circuit, a low frequency content detection circuit, and an output chopping circuit electrically connected in a cascade. The low frequency content detection circuit operates in combination with a transconductance or other gain circuit as a high pass filter that filters input offset voltage and/or low frequency noise of the amplification circuit, thereby suppressing output chopping ripple from arising.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Linear Technology Holding LLC
    Inventors: Alex R. Sloboda, Gregory L. DiSanto, Andrew K. Roberts
  • Patent number: 10673390
    Abstract: Devices, systems and methods for clamping output voltages of op-amps while minimizing post-clamping recovery delays are described. A circuit, which controls transitions between two operating modes, may include a first comparator for comparing an output voltage with a clamping voltage and outputting a first mode signal, a second comparator for comparing an input voltage with a reference voltage and outputting a second mode signal. A first logic component may receive the mode signals, perform a logical operation, and output a logic signal. A duplex output, based on a value of the logic signal, may output a track signal and an inversely corresponding hold signal, such track and hold signals being used by an op-amp circuit to configure adjusting blocks used to control transients during mode transitions.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 2, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Marc Henri Ryat
  • Patent number: 10673398
    Abstract: An electronic circuit comprises an input stage, a gain stage operatively coupled to the input stage, a primary output stage operatively coupled to the gain stage, a replica output stage operatively coupled to the gain stage in parallel to the primary output stage, and a clock circuit. The clock circuit operates the electronic circuit in multiple phases including a sampling phase to disconnect the primary output stage and the replica output stage from the gain stage to obtain an offset voltage, an active phase to reconnect the primary output stage to apply the offset voltage to reduce an offset at the primary output stage, and an intermediate phase to first reconnect the replica output stage to the gain stage prior to the active phase.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10666213
    Abstract: The invention relates to an amplification circuit (100), comprising: a VGA (2), an AGC loop (10) for automatically controlling the gain of the VGA (2), a switching circuit (14) for switching between an AGC mode, in which the gain of the VGA (2) is automatically controlled by an output signal of the AGC loop (10) and a manual gain control, MGC, mode, in which the gain of the VGA (2) can be manually controlled by an input signal, and a read/write circuit (30) with a contact (31) for connection to a peripheral system, wherein the read/write circuit (30) is configured, in the MGC mode, to provide the input signal from the contact (31) via a write-mode path (32) to the VGA (2), and, in the AGC mode, to provide the output signal of the AGC loop (10) via a read-mode path (33) on the contact (31).
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 26, 2020
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Ahmed Awny, Alexey Balashov, Dietmar Kissinger
  • Patent number: 10658992
    Abstract: A circuit for implementing an operational transconductance amplifier (OTA) based on telescopic topology, wherein cascode transistors of the operational transconductance amplifier (OTA) are self-biased without using additional biasing circuitry, which not only reduces power consumption but also achieves high gain without extra current, and each cascode stage of the OTA has a pair of transistors so that the swing of the output differential signals of the OTA can be completely symmetrical so as to benefit second-order harmonic rejection, CMRR and PSRR.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Rafael Microelectronics, Inc.
    Inventor: Tzu-Yun Wang
  • Patent number: 10658997
    Abstract: A voltage controlled amplifier with an amplitude limiting circuit, such as a clip limiter, that is separate from the signal path on which the input signal is received by a power amplifier can reduce both noise and power expenditure of the voltage controlled amplifier. The amplitude limiting circuit can include a transistor network that is controlled by a pair of utility operational amplifiers. These utility amplifiers may use less current than the audio amplifier of the voltage controlled amplifier. Further, the transistor network can be deactivated when a signal supplied to the voltage controlled amplifier is below a clipping or other voltage limiting threshold.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 19, 2020
    Assignee: RGB Systems, Inc.
    Inventor: Eric Mendenhall