Abstract: A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.

Abstract: A receiver front-end circuit and an operating method thereof are disclosed. The receiver front-end circuit includes a common-mode suppression circuit and a rear-stage circuit. The common-mode suppression circuit is used to receive an external input common-mode voltage signal and perform common-mode noise suppression processing on the external input common-mode voltage signal, and then output an internal input common-mode voltage signal. The rear-stage circuit is coupled to the common-mode suppression circuit and used to receive the internal input common-mode voltage signal. The dynamic swing of the internal input common-mode voltage signal is smaller than the dynamic swing of the external input common-mode voltage signal.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An amplifier is provided. The amplifier includes a first resistor electrically connected to the input terminal, a second resistor electrically connected to the output terminal, a switch including a metal-oxide-semiconductor field-effect transistor (MOSFET) and electrically connected to one end of the second resistor, and a switch control processor configured to electrically connect the gate terminal of the MOSFET constituting the switch and the bulk terminal of the MOSFET constituting the switch to an impedance having an impedance value higher than a preset first threshold.

Abstract: Disclosed is an electronic device including a power amplifier (PA) configured to amplify a transmission signal, a matching circuit configured to be connected with the PA and to form a load impedance, a filter configured to be connected with the matching circuit, and a control circuit configured to control a state of at least one of a bias of the PA, the matching circuit, and the filter. The control circuit may identify a network to which the electronic device is connected among a first network and a second network and may operate the matching circuit in one of a first state, a second state, and a third state based on the identified network.

Abstract: In one embodiment, an amplifier circuit may be configured with an output transistor that forms an output current and an output voltage at an output. The amplifier circuit may also include a reference circuit that may be configured to form a reference current that is substantially proportional to the output current. An embodiment of the reference circuit may also be configured to control a transistor to sink current from the output in response changes in the reference current.

Abstract: An amplifier includes a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT) with “hard saturation.”; where the FET or the BJT to has a nearly constant drain or collector current when the drain or collector voltage is greater than the pinchoff voltage. The amplifier further includes a bias network, configured to provide a DC voltage to the FET or the BJT, a means for isolating the DC voltage from the matching network, an electrical load, and a matching network which transforms the electrical load to a resistance between the drain and the source or the collector and emitter which causes the drain or collector voltage to be greater than the pinchoff voltage over the entire cycle of the sinusoidal voltage applied to the gate, whereby the amplifier is linear.

Abstract: A supply modulator is provided, having a first amplifier circuit configured to generate a first electrical signal, a second amplifier circuit configured to generate a second electrical signal, the first and second electrical signals being for driving an electrical load, and a control circuit electrically coupled to the first and second amplifier circuits wherein the control circuit is configured to generate a pulsed electrical signal and to supply an output control signal to the second amplifier circuit for controlling generation of the second electrical output signal, wherein the supply modulator is configured to operate in two modes of operation, for the first amplifier circuit to generate the first electrical signals in response to quiescent current of the first amplifier circuit, for the control circuit to generate a modulated electrical signal in accordance with a clock signal in one mode, and, for the second amplifier circuit to operate.

Abstract: A system for adjusting bias power provided to a radio-frequency amplifier to increase plurality of figures of merit based on sensed characteristics of the amplifier and/or characteristics of the input or output power.

Abstract: An amplifier may comprise first and second matching networks; first and second transistors; and a transformer including first to third inductors. Also, a gate and a source of the first transistor are connected to the first matching network, one end of the first inductor is connected to a drain of the first transistor, the other end of the first inductor is connected to a source of the second transistor, one end of the second inductor is connected to a gate of the second transistor, the other end of the second inductor is grounded, one end of the third inductor is connected to a drain of the second transistor, and the other end of the third inductor is connected to the second matching network.

Abstract: An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An amplifier is provided. The amplifier includes a first resistor electrically connected to the input terminal, a second resistor electrically connected to the output terminal, a switch including a metal-oxide-semiconductor field-effect transistor (MOSFET) and electrically connected to one end of the second resistor, and a switch control processor configured to electrically connect the gate terminal of the MOSFET constituting the switch and the bulk terminal of the MOSFET constituting the switch to an impedance having an impedance value higher than a preset first threshold.

Abstract: An amplifier circuit is a cascade amplifier circuit that includes a first transistor circuit including a signal input portion to which a signal is input from outside; a load circuit connected between the first transistor circuit and a power-supply line; and a second transistor cascode-connected between the load circuit and the first transistor circuit. The first transistor circuit is constituted by a plurality of transistors connected in parallel, and a bias circuit is provided that selectively supplies a bias voltage to the plurality of transistors.

Abstract: A variable gain amplifier device includes a variable gain amplifier circuitry and a control voltage generating circuitry. The variable gain amplifier circuitry is configured to amplify input signals to generate output signals, wherein the variable gain amplifier circuitry includes a gain setting circuit that is configured to set a gain of the variable gain amplifier circuitry according to a control voltage. The control voltage generation circuitry is configured to simulate at least one circuit portion of the variable gain amplifier circuitry, in order to generate the control voltage according to the input signals and a setting voltage.

Abstract: Radio Frequency (RF) amplifier design with RFIC suffers gain variations from gain variations due to wafer process variations, temperature changes, and supply voltage changes. Three methods are proposed to achieve constant amplifier gain, either through on-chip wafer calibration, or self-calibration. Through automatic adjustment of amplifier bias current, the proposed methods maintain constant amplifier gain over process, temperature, supply voltage variations. Under the proposed Method 1, a constant transconductance Gm with enhanced gain accuracy is maintained via wafer calibration. Under the proposed Method 2, a constant transconductance Gm is maintained by time-domain averaging through different transistors. Under the proposed Method 3, a constant Gm*R or RF gain is maintained considering the impedance of a matching network of the RF amplifier.

Abstract: A Doherty amplifier circuit having a tunable impedance and phase (“TIP”) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance ZINV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90° (for a selected polarity)±a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90° (at the selected polarity).

Abstract: A power amplifier circuit includes a first transistor; a first bias circuit that supplies a first bias current or voltage; a capacitor; a first inductor; a second inductor; a second transistor; a second bias circuit that supplies a second bias current or voltage; a third inductor; a third transistor; a third bias circuit that supplies a third bias current or voltage; and a fourth inductor.

Abstract: A system may include a forward signal path having a forward gain and configured to receive an input signal at an input and generate an output signal at an output as a function of the input signal, a feedback signal path having a feedback gain and coupled between the output and the input, and a control subsystem configured to operate the forward signal path and the feedback signal path in at least two modes comprising a first mode in which the forward gain is a first forward gain and the feedback gain is a first feedback gain and a second mode in which the forward gain is a second forward gain smaller than the first forward gain and the feedback gain is a second feedback gain larger than the first feedback gain. The control subsystem may cause operation in the first mode when signal content is present in the input signal and may cause operation in the second mode when signal content is absent from the input signal.

Abstract: Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

Abstract: A supply voltage conditioning circuit comprises a differential amplifier, a comparator, a sample and hold (S/H) circuit, and a delay circuit. The differential amplifier receives an input supply voltage and a reference voltage, and outputs a difference signal. The comparator receives the difference signal and a value representative of a noise margin, and outputs a control signal indicative of whether the difference signal is greater than the value representative of the noise margin. The S/H circuit samples the input supply voltage in response to the control signal indicating the difference signal is greater than the noise margin, and outputs a substantially noise free supply voltage. This allows the output supply voltage to track underlying changes in the input supply voltage but filter out noise in the input supply voltage. The delay circuit receives and delays the output supply voltage to generate the reference voltage.

Abstract: Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.