Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers include a stack of word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer. Drain-select-level openings are formed through the at least one drain-select-level sacrificial material layer, which is replaced with at least one drain-select-level electrically conductive layer. Memory openings are formed by vertically extending the drain-select-level openings through the word-line-level sacrificial material layers. Memory opening fill structures are formed within the memory openings. The word-line-level sacrificial material layers are replaced with word-line-level electrically conductive layers.

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

Abstract: An integrated circuit device includes a peripheral circuit structure including a lower substrate, an arc protection diode in the lower substrate, and a common source line driver connected to the arc protection diode, a conductive plate on the peripheral circuit structure, a cell array structure overlapping the peripheral circuit structure in a vertical direction with the conductive plate therebetween, and a first wiring structure connected between the arc protection diode and the conductive plate.

Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Abstract: A method for forming a semiconductor device includes forming a conductive contact over a semiconductor substrate, and forming a first dielectric layer covering the conductive contact. The method also includes partially removing the first dielectric layer to form an opening exposing a top surface of the conductive contact, and forming a bottom electrode covering sidewalls of the opening and the top surface of the conductive contact. The method further includes depositing a second dielectric layer over the bottom electrode using a first process, and depositing dielectric portions over the second dielectric layer and at top corners of the opening using a second process. The first process has a first step coverage, the second process has a second step coverage, and the second step coverage is smaller than the first step coverage. The method includes forming a top electrode covering the second dielectric layer and the dielectric portions.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

Abstract: A neuron device is described. The neuron device is based on spontaneous polarization switching which includes a plurality of gate electrodes, a plurality of drain electrodes, a plurality of source lines, a dielectric layer, and a semiconductor layer. The gate electrodes are arranged parallel to each other. The drain electrodes are arranged parallel to each other. The source lines are arranged between the gate electrodes and the drain electrodes and parallel to each other. The dielectric layer is formed at intersections between the gate electrodes and the source lines. The semiconductor layer is formed at intersections between the drain electrodes and the source electrodes. The drain electrodes function as synapse-after-neuron linking terminals. The gate electrodes adjust an arrangement direction of electrical dipoles of the dielectric layer to control a firing time point and a firing height of the neuron device.

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes bit line contact structures, bit line structures, first insulating structures, a capacitor contact structure, a first connecting pad, a second insulating structure, and a capacitor structure. The bit line structure extends along a first direction. The first insulating structure extends along a second direction that intersects the first direction. The capacitor contact structure is located between two of the bit lines and two of the first insulating structures. The first connecting pad is formed on the capacitor contact structure. The second insulating structure surrounds the first connecting pad, in which the top width of the second insulating structure is greater than the bottom width thereof.

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Abstract: Heterostructures include a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions.

Abstract: A nitride compound semiconductor having a low resistivity that is conventionally difficult to be manufactured is provided. Since the nitride compound semiconductor exhibits a high electron mobility, a high-performance semiconductor device may be configured. The present invention may provide, at a high productivity, a group 13 nitride semiconductor of an n-type conductivity that may be formed as a film on a substrate having a large area size and has a mobility of 70 to 140 cm2/(V·s) by a pulsed sputtering method performed in a process atmosphere at room temperature to 700° C.

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a spacer structure on a sidewall of the bit line structure, a contact plug structure contacting the spacer structure, an insulating interlayer structure partially penetrating through upper portions of the contact plug structure, the spacer structure and the bit line structure, and a capacitor on the contact plug structure. The spacer structure includes an air spacer including air. The insulating interlayer structure includes first and second insulating interlayers. The second insulating interlayer may include an insulation material different from that of the first insulating interlayer. A lower surface of the second insulating interlayer covers a top of the air spacer, and a lowermost surface of the first insulating interlayer is covered by the second insulating interlayer.

Abstract: The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.

Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

Abstract: Heterostructures include a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions.

Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.