Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second insulator provided between the first insulator and the first oxide, a second oxide in contact with the first insulator and in contact with a side surface of the first oxide, and a third insulator over the first insulator, the second oxide, and the first oxide. The third insulator includes a region in contact with a top surface of the first oxide. The second insulator and the third insulator include a material which is less likely to pass oxygen than the second oxide.

Abstract: A light emitting device package includes a cell array having a first surface and a second surface located opposite to the first surface and including, on a portion of a horizontal extension line of the first surface, semiconductor light emitting units each including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially located on a layer surface including a sidewall of the first conductivity type semiconductor layer; wavelength converting units corresponding respectively to the semiconductor light emitting units and each arranged corresponding to the first conductivity type semiconductor layer; a barrier structure arranged between the wavelength converting units corresponding to the cell array; and switching units arranged in the barrier structure and electrically connected to the semiconductor light emitting units.

Abstract: A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.

Abstract: A thin film transistor includes a gate electrode, an insulating layer disposed on the gate electrode, and an active layer disposed on the insulating layer, where the active layer includes a perovskite compound represented by the following Formula: AB(1-u)C(u)[X(1-v)Y(v)]3, where A is a monovalent organic cation, a monovalent inorganic cation, or any combination thereof, B is Sn2+, C is a divalent cation or trivalent cation, X is a monovalent anion, Y is a monovalent anion different from X, u is a real number greater than 0 and less than 1, and v is a real number greater than 0 and less than 1.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and stack dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall of the part of the doped portion of the semiconductor channel that extends beyond the stack structure.

Abstract: A semiconductor memory device and a method of forming the same include a substrate, bit lines, contacts, a dielectric layer, storage node pads and a capacitor structure. The bit lines are disposed on the substrate and include a plurality of first bit lines and at least one second bit line. The contacts are disposed on the substrate and alternately and separately disposed with the bit lines. The dielectric layer is disposed over the contacts and bit lines. The storage node pads are disposed in the dielectric layer and respectively contact the contacts. The capacitor structure is disposed on the storage node pads and includes a plurality of first capacitors and at least one second capacitor located above at least one second bit line. Therefore, the semiconductor memory device can achieve more optimized device performance.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

Abstract: A micro-semiconductor chip wet alignment apparatus is provided. The micro-semiconductor chip wet alignment apparatus includes a semiconductor chip wet supply module configured to supply the plurality of micro-semiconductor chips and a liquid onto the transfer substrate so that the plurality of micro-semiconductor chips are flowable on the transfer substrate; and a chip alignment module including an absorber capable of relative movement along a surface of the transfer substrate and configured to absorb the liquid so that the plurality of micro-semiconductor chips are aligned in the plurality of grooves.

Abstract: Methods, systems and apparatus for managing driving connection structures of memory devices, e.g., three-dimensional memory devices. In one aspect, a semiconductor device includes: a first array structure of memory cells including first conductive layers, a second array structure of memory cells including second conductive layers, a connection structure arranged between the first and second array structures along a first direction, and a circuit arranged adjacent to the connection structure. The connection structure includes: first and second connection areas through which the first and second conductive layers are electrically connectable to the circuit, a first stepped structure configured to individually expose the first conductive layers in the first array structure, a second stepped structure configured to individually expose the second conductive layers in the second array structure.

Abstract: A display substrate has an active area and a frame region located at at least one side of the active area. The display substrate includes a substrate, pixel units, at least one blocking dam and a first encapsulation layer. The pixel units is disposed on the substrate and located in the active area. The at least one blocking dam is disposed on the substrate and located in the frame area. The at least one blocking dam is provided with at least one groove on a surface thereof facing away from the substrate, a depth direction of the at least one groove is perpendicular to the substrate, and an extending direction of the at least one groove is substantially the same as an extending direction of the blocking dam provided with the at least one groove. The first encapsulation layer covers the at least one blocking dam.

Abstract: A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

Abstract: A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.

Abstract: A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads.

Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.