Abstract: Apparatuses and methods for controlling hydrogen supply in manufacturing memory devices are described. An example apparatus includes: a first capacitor disposed above a substrate; a hydrogen supply film above the first capacitor; a second capacitor above the hydrogen supply film; and a barrier film between the hydrogen supply film and the second capacitor. The hydrogen supply film provides hydrogen and/or hydrogen ions. The barrier film is hydrogen-impermeable.

Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.

Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.

Abstract: An electronic device is provided, including a substrate, a plurality of bonding pads, and a plurality of light emitting members. The bonding pads are disposed on the substrate. The light emitting members are disposed on the bonding pads. The light emitting members include a first pair of adjacent light-emitting members, a second pair of adjacent light-emitting members, and a third pair of adjacent light-emitting members. The first pair of adjacent light-emitting members, the second pair of adjacent light-emitting members, and the third pair of adjacent light-emitting members are arranged along the first direction in sequence. The first pair of adjacent light-emitting members has a first pitch, the second pair of adjacent light-emitting members has a second pitch, and the third pair of adjacent light-emitting members has a third pitch. The third pitch is greater than the second pitch, and the second pitch is greater than the first pitch.

Abstract: The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

Abstract: The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields can influence properties of the two-dimensional material, including carrier density, transport properties, optical properties, surface chemistry, piezoelectric-induced strain, magnetic properties, and interlayer spacing. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided, including tunable sensors, optical emitters, and programmable logic gates.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate comprising one or more isolation features defining active regions; forming at least one access transistor comprising a plurality of impurity regions, wherein the impurity regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated impurity region; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first and second contact holes.

Abstract: A semiconductor device includes a plurality of first conductive patterns extending parallel in a first direction on a substrate, a plurality of second conductive patterns extending parallel in a second direction crossing the first direction on the substrate, a plurality of buried contacts connected to the substrate between the plurality of first conductive patterns and between the plurality of second conductive patterns, and a landing pad connected to each of the buried contacts on the plurality of buried contacts. The landing pad includes a first side surface extending in the first direction in plan view and a second side surface extending in a third direction in plan view. The third direction is different from the first direction and the second direction in plan view.

Abstract: A substrate processing apparatus includes a chuck configured to attract and hold a substrate; an observer configured to observe multiple positions within a second surface of the substrate attracted to and held by the chuck, the second surface being opposite to a first surface thereof which is in contact with the chuck; and an analyzer configured to analyze observation results of the multiple positions. When a singularity regarding a height from a surface of the chuck attracting and holding the substrate exists on the second surface, the analyzer specifies a position of the singularity on the chuck.

Abstract: Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same, wherein the capacitor may include a first conductive layer, a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines.

Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.

Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Abstract: Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height from an LED base and including a plurality of epitaxial layers including a first n-layer, a first active layer, and a first p-layer. A second flat region is provided, at a second height from the LED base and parallel to the first flat region, and includes at least a second n-layer. A sloped sidewall connecting the first flat region and the second flat region is provided and includes at least a third n-layer, the first n-layer being thicker than at least a portion of third n-layer. A p-contact is formed on the first p-layer and an n-contact formed on the second n-layer.

Abstract: A method for manufacturing a dynamic random access memory includes: forming a buried bit line in a substrate; forming a plurality of buried word lines in the substrate, wherein the bottom surfaces of the buried word lines are higher than the top surface of the buried bit line; forming a bit line contact structure on the buried bit line; forming a through hole passing through the bit line contact structure, wherein the bit line contact structure is not in direct contact with the buried bit line, and the material of the bit line contact structure is different from the material of the buried bit line; forming a conductive plug between the bit line contact structure and the buried bit line; and forming a capacitor structure on the substrate.

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

Abstract: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.