Abstract: A photocoupler of an embodiment includes an input terminal, an output terminal, a first MOSFET, a second MOSFET, a semiconductor light receiving element, a semiconductor light emitting element, and a resin layer. The first MOSFET is joined onto the third lead. The second MOSFET is joined onto the fourth lead. The semiconductor light receiving element is joined to each of the first junction region and the second junction region. The semiconductor light receiving element includes a light receiving region provided in a central part of a surface on opposite side from a surface joined to the first and second MOSFET. The resin layer seals the first and second MOSFETs, the semiconductor light receiving element, the semiconductor light emitting element, an upper surface and a side surface of the input terminal, and an upper surface and a side surface of the output terminal.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a substrate comprising an array area and a peripheral area adjacent to the array area; word line structures positioned in the array area; a word line hard mask layer positioned on the array area; a word line protection layer positioned on the word line hard mask layer; a gate electrode layer positioned on the peripheral area and separated from the word line hard mask layer and the word line protection layer; a peripheral protection layer positioned on the to gate electrode layer; and a first hard mask layer positioned over the array area and the peripheral area. A horizontal distance between the word line protection layer and the gate electrode layer is greater than or equal to three times of a thickness of the first hard mask layer.

Abstract: An apparatus for measuring electrical potentials of a liquid sample includes at least one field effect transistor having a source, a drain, and a gate, a substrate, and at least two intersecting nanowires of semiconductive material arranged on the substrate, each having a source and drain contact as a field effect transistor and a voltage applicator configured to apply a voltage between the respective source and drain contact. The cross section of the two nanowires has a shape of a triangle or a trapezium. A voltage applicator configured to apply a voltage to the substrate are arranged on the substrate. The nanowires are electrically insulated at least against the sample by a dielectric layer along their surface having a layer thickness between 5 and 40 nm, and at least one impurity is arranged in the dielectric layer as a bearing point which is capable of capturing charge carriers.

Abstract: A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

Abstract: A semiconductor device is provided, including a buried oxide layer, having a first side and a second side. A silicon-based device layer is disposed on the first side of the buried oxide layer. The silicon-based device layer includes a first interconnection structure. A semiconductor-based device layer is disposed on the second side of the buried oxide layer. The semiconductor-based device layer includes a second interconnection structure.

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

Abstract: A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

Abstract: A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

Abstract: A photodetecting device includes a substrate, a first photosensitive layer supported by the substrate, and a second photosensitive layer supported by the substrate and adjacent to the first photosensitive layer, each of the first photosensitive layer and the second photosensitive layer being coupled to a first doped portion having a first conductivity type, and a second doped region having a second conductivity type different from the first conductivity type, wherein the first photosensitive layer is separated from the second photosensitive layer, and the first doped portion coupled to the first photosensitive layer is electrically connected to the first doped portion coupled to the second photosensitive layer.

Abstract: Sensors having an advantageous design and methods for fabricating such sensors are generally provided. Some sensors described herein comprise pairs of electrodes having radial symmetry, pairs of nested electrodes, and/or nanowires. Some embodiments relate to fabricating electrodes by methods in which nanowires are deposited from a fluid contacted with a substrate in a manner such that it evaporates and is replenished.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.

Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.

Abstract: The application provides a display substrate and a display device. The display substrate includes: gate lines, data lines, the gate lines and the data lines being arranged to intersect to define sub-pixels, every multiple sub-pixels in a same row constituting a pixel unit; and common electrode lines, each of the common electrode lines is between adjacent two of the gate lines. The display substrate further includes common voltage input line groups intersecting with the common electrode lines. Common voltage input lines in different groups are electrically connected to different ones of the common electrode lines, respectively; and an orthographic projection of every N columns of pixel units on a substrate covers an orthographic projection of a corresponding one of the common voltage input line groups on the substrate, where N is an integer greater than or equal to 1.

Abstract: An eighth semiconductor portion is provided between the first semiconductor portion and the third semiconductor portion. The eighth semiconductor portion is of the second conductivity type, contacting the first semiconductor portion, and having a lower second-conductivity-type impurity concentration than the second semiconductor portion.

Abstract: The present disclosure provides a semiconductor device with a composite dielectric structure and a method for forming the semiconductor device. The semiconductor device includes a conductive contact disposed over a semiconductor substrate, and a first dielectric layer disposed over the conductive contact. A top surface of the conductive contact is exposed by an opening. The semiconductor device also includes a bottom electrode extending along sidewalls of the opening and the top surface of the conductive contact, and a top electrode disposed over the bottom electrode and separated from the bottom electrode by a dielectric structure. The dielectric structure includes a second dielectric layer and dielectric portions disposed over the second dielectric layer. The dielectric portions cover top corners of the opening and extend partially along the sidewalls of the opening.

Abstract: Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.