Abstract: The present application discloses a method for fabricating a semiconductor device with a protruding contact. The method includes providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing a top surface of the bit line structure; and forming a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Abstract: One example method of operation may include creating a force approximation of a number of nodes in a defined space at an initial time (t0), the force approximation being based on a data realization simulation model of an n-body simulation, where n is an integer greater than one. The method may also include determining initial displacement changes of one or more of the nodes within the defined space has occurred in the force approximation, summing the initial displacement changes of the one or more of the nodes to create a summed total displacement, creating an initial displacement threshold (Td) based on the summed total displacement.

Abstract: A semiconductor integrated circuit includes a high-potential-side circuit region, a high-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region via the high-voltage junction termination structure which are integrated into a single chip, and wherein a first distance between a looped well region and a buried layer in a region in which a first contact region is formed is smaller than a second distance between the looped well region and the buried layer in a region in which a carrier reception region is formed.

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane parallel with the surface of the semiconductor substrate that are unequal with one another. The semiconductor pillar structure can have a cross-section parallel with the semiconductor substrate surface that is in the shape of a: rectangle; oval elongated polygon, etc. The length of the longer dimension can be adjusted to provide a desired amount of current though the semiconductor pillar structure to drive the two-terminal resistive memory element.

Abstract: An electronic device is provided, including a substrate, a plurality of bonding pads, and a plurality of light emitting members. The bonding pads are disposed on the substrate. The light emitting members are disposed on the bonding pads. The light emitting members include a first pair of adjacent light-emitting members, a second pair of adjacent light-emitting members, and a third pair of adjacent light-emitting members. The first pair of adjacent light-emitting members, the second pair of adjacent light-emitting members, and the third pair of adjacent light-emitting members are arranged along the first direction in sequence. The first pair of adjacent light-emitting members has a first pitch, the second pair of adjacent light-emitting members has a second pitch, and the third pair of adjacent light-emitting members has a third pitch. The third pitch is greater than the second pitch, and the second pitch is greater than the first pitch.

Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

Abstract: An organic light-emitting diode (OLED) display panel and a display device are provided. The OLED display panel includes first pixel units and second pixel units that are arranged symmetrically-mirrored to each other. A longitudinal direction of pixel electrode of each pixel unit is parallel to a longitudinal direction of the OLED display panel. Blue sub-pixels of each pixel unit are individually arranged in a row, and red sub-pixels and green sub-pixels are arranged together in another row, so as to alleviate technical problems where a pixel arrangement of traditional hybrid arrangement OLED panels restricts printing method.

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

Abstract: An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

Abstract: A memory device includes a semiconductor substrate having a first active region and a second active region adjacent to the first active region. The memory device also includes a first word line extending across the first active region and the second active region. The memory device further includes a first source/drain region in the first active region and a second source/drain region in the second active region disposed at opposite sides of the first word line. In addition, the memory device includes a first capacitor disposed over and electrically connected to the first source/drain region in the first active region, and a second capacitor disposed over and electrically connected to the second source/drain region in the second active region. The first capacitor and the second capacitor have different sizes.

Abstract: Systems and methods automatically construct a realization of a model from an available set of alternative co-simulation components, where the realization meets one or more objectives, such as fidelity, execution speed, or memory usage, among others. The systems and methods may construct the realization model by setting up and solving a constrained optimization problem, which may select particular ones of the alternative co-simulation components to meet the objectives. The systems and methods may configure the realization, and execute the realized model through co-simulation. The systems and methods may employ and manage different execution engines and/or different solvers to run the realization of the model.

Abstract: The present disclosure provides an active pixel sensing circuit structure, an active pixel sensor, a display penal and a display device, aiming to reduce an area of the active pixel sensing circuit structure. A control electrode of a second transistor in the active pixel sensing circuit structure is located in a first metal layer. A first voltage signal line, a second voltage signal line, and an output signal line are located in a second metal layer that is located on a side of the first metal layer facing away from the substrate. A first electrode of a photodiode is connected to the control electrode of the second transistor through a first connection line. The first connection line is located in a third metal layer that is located on a side of the second metal layer facing away from the substrate.

Abstract: A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor device comprises: a first active region over a substrate; and a first bit line structure intercepting the first active region at a level that is lower than a top-most surface thereof, the first bit line structure including a barrier liner having a U-profile in a width direction thereof in electrical contact with the first active region.

Abstract: A method of depositing a material film on a substrate within a reaction chamber by a cyclical deposition process is disclosed. The method may include: contacting the substrate with a first vapor phase reactant and purging the reaction chamber with a first main purge. The method also includes: contacting the substrate with a second vapor phase reactant by two or more micro pulsing processes, wherein each micro pulsing process comprises: contacting the substrate with a micro pulse of a second vapor phase reactant; and purging the reaction chamber with a micro purge, wherein each of the micro pulses of the second vapor phase reactant provides a substantially constant concentration of the second vapor phase reactant into the reaction chamber. The method may also include; purging the reaction chamber with a second main purge. Device structures including a material film deposited by the methods of the disclosure are also disclosed.

Abstract: A microelectronic device comprises a semiconductive pillar structure comprising a central portion, a first end portion, and a second end portion on a side of the central portion opposite the first end portion, the first end portion oriented at an angle with respect to the central portion and extending substantially parallel to the second end portion, a digit line contact on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: The present disclosure provides a semiconductor device and its preparation method, wherein the preparation method includes providing a substrate, forming bit line units, capacitor contacts and a conductive layer on the substrate, patterning the conductive layer on the substrate by step-by-step etching, etching first grooves to form first conductive parts positioned above the bit line units, protecting sidewalls of the first grooves, and then etching second grooves to form second conductive parts covering sidewalls of the bit line units and third conductive parts covering the capacitor contacts.

Abstract: A method including forming a first member having a first portion including a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member of a concave shape having a third portion, which corresponds to a lower top surface of the concave shape, including a plurality of access transistors provided correspondingly to the plurality of storage capacitors therein and a fourth portion, which corresponds to an upper top surface of the concave shape, surrounding the third portion; stacking the first member on the second member to physically connect the second and fourth portions and have a gap between the first and third portions; cutting the first member to physically separate the first portion from the second portion; and joining the separated first portion and the third portion with filling the gap therebetween.

Abstract: A cable driving a large system such as cable driven machines, cable cars or tendons in a human or robot is typically modeled as a large number of small segments that are connected via joints. The two main difficulties with this model are satisfying the inextensibility constraint and handling the typically large mass ratio between the segments and the objects they connect. This disclosure introduces an effective approach to solving these problems. The introduced approach simulates the effect of a cable using a new type of distance constraint called ‘cable joint’ that changes both its attachment points and its rest length dynamically. The introduced approach models a cable connecting a series of objects, e.g., components of a robot, as a sequence of cable joints, reducing the complexity of the simulation from the order of the number of segments in the cable to the number of connected objects.