Patents Examined by Steven Sawyer
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Patent number: 8422240Abstract: An electronic apparatus includes a flexible printed circuit having a first surface on which a switch is mounted, a reinforcement plate having a first surface arranged to face a second surface of the flexible printed circuit opposite to the first surface of the flexible printed circuit on which the switch is mounted, and a spacer arranged to face a second surface of the reinforcement plate opposite to the first surface of the reinforcement plate that faces the second surface of the flexible printed circuit.Type: GrantFiled: July 27, 2010Date of Patent: April 16, 2013Assignee: Panasonic CorporationInventor: Jun Saiki
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Patent number: 8422247Abstract: An electric apparatus module 1 includes an upper casing 6, a lower casing 7 to which the upper casing 6 is attached and which is attached to a rear panel 2, an electronic device unit 8 accommodated in the upper casing 6 and the lower casing 7, a conductive shield shell 9 covering the electronic device unit 8, and a conductive ground shell 10 which is attached to the lower casing 7 at a side of the rear panel 2. The ground shell 10 includes a flat plate portion 83 piled on the rear panel 2, a contact piece 84 erected from an outer edge 83c of the flat plate portion 83 toward the lower case 7, and a contact member 85 protruded from a rear surface 83b of the flat plate portion 83 at the side of the rear panel 2. The contact piece 84 is inserted through a through hole 56 formed on the lower casing 7 to contact with the shield shell 9. The contact member 85 is inserted through a through hole 11 formed on the rear panel 2 to contact a cylindrical shield member 22 of an external device.Type: GrantFiled: May 21, 2009Date of Patent: April 16, 2013Assignee: Yazaki CorporationInventor: Isao Kameyama
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Patent number: 8411447Abstract: A power amplifier chassis for an n+1 redundant power amplifier system. The power amplifier chassis includes an embedded controller and a power amplifier. The embedded controller operates the power amplifier chassis in a master controller mode or a slave controller mode. When operated in the master controller mode, the embedded controller monitors operating parameters associated with the power amplifier chassis, and can transfer control of the power amplifier system when the embedded controller senses that the monitored operating parameters indicate a failure or impending failure of the power amplifier chassis. When operated in the slave controller mode, the embedded controller receives control instructions from the master controller power amplifier module, and is enabled to reconfigure the power amplifier chassis from the slave controller mode to the master controller mode in response to a failure or imminent failure indication of a first power amplifier chassis operated in master controller mode.Type: GrantFiled: December 18, 2009Date of Patent: April 2, 2013Assignee: Teledyne Paradise Datacom, LLCInventor: Stephen D. Turner
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Patent number: 8410372Abstract: A wiring board to be inserted between collector foils of each unit cell in a stacked battery includes a comb-shaped insulating substrate and a wiring layer. The insulating substrate has a plurality of teeth and a rod, and the wiring layer is formed on the insulating substrate and includes a plurality of lead wires individually extending from a distal end of each of the plurality of teeth to an end of the rod to deliver a current of a potential across a conductive member being in contact with the distal ends of the teeth to the end of the rod.Type: GrantFiled: November 21, 2007Date of Patent: April 2, 2013Assignee: Nissan Motor Co., Ltd.Inventors: Takuya Kinoshita, Kenji Hosaka, Hajime Satou, Osamu Shimamura
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Patent number: 8406009Abstract: An electronic device is provided, the electronic device includes a printed circuit board (PCB) having a mounting point. The computer system also includes a chassis having a mounting post. The mounting point and the mounting post are flexibly connected.Type: GrantFiled: January 30, 2008Date of Patent: March 26, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jeffrey A. Lev, Steven S. Homer, Earl W. Moore, Mark H. Ruch
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Patent number: 8406008Abstract: A portable electronic device includes a main housing, a metal frame, and at least one metal elastic member. The main housing includes a peripheral wall. The peripheral wall defines a recessed portion and includes at least one latching portion at the recessed portion. The metal frame clips the peripheral wall in the recessed portion. The at least one elastic member is detachably attached to the at least one latching portion. The at least one elastic member electronically connects the metal frame to the housing.Type: GrantFiled: June 15, 2010Date of Patent: March 26, 2013Assignees: Shenzhen Futaihong Precision Industry Co., Ltd., FIH (Hong Kong) LimitedInventor: De-Zhi Han
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Patent number: 8405999Abstract: A flexible wiring board includes a first flexible base material with a conductor pattern formed thereon, a second flexible base material disposed adjacent to the first flexible base material and an insulating layer covering the first flexible base material and the second flexible base material. The insulating layer exposes at least one portion of the first flexible base material. A conductor pattern is formed on the insulating layer, and a plating layer is provided connecting the conductor pattern of the first flexible base material and the conductor pattern on the insulating layer.Type: GrantFiled: March 10, 2009Date of Patent: March 26, 2013Assignee: Ibiden Co., Ltd.Inventor: Michimasa Takahashi
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Patent number: 8400784Abstract: Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.Type: GrantFiled: August 10, 2009Date of Patent: March 19, 2013Assignee: Silergy TechnologyInventor: Budong You
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Patent number: 8395906Abstract: A high-speed transmission circuit board connection structure includes a first high-speed transmission circuit board including a laminated substrate including a first signal transmission wiring formed on a surface thereof and a ground plane formed inside thereof, a second high-speed transmission circuit board including a circuit substrate and a second signal transmission wiring formed on a surface of the circuit substrate, a conductive board connecting member for fixing the first and second high-speed transmission circuit boards to a surface thereof, and a bonding wire for electrically connecting the first signal transmission wiring and the second signal transmission wiring. The ground plane is exposed on a side end face of the laminated substrate, and a conductive film is formed on the side end face such that the ground plane of the first high-speed transmission circuit board is electrically connected to the board connecting member with the conductive film.Type: GrantFiled: June 1, 2010Date of Patent: March 12, 2013Assignee: Hitachi Cable, Ltd.Inventors: Masayuki Nikaido, Yoshiaki Ishigami, Kenichi Tamura, Takehiko Tokoro
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Patent number: 8389867Abstract: For the purpose of providing a semiconductor element built-in type multilayered circuit board in which a semiconductor element is closely joined to a recess of an insulating substrate to effectively disperse heat generated from the semiconductor element through the insulating substrate at a working temperature region of the semiconductor element circuit board, to surely conduct an electrical connection of an electronic part such as semiconductor element or the like in a short wiring and to enable the high density mounting of semiconductor elements, miniaturization and increase of working speed, there is proposed a semiconductor element built-in type multilayered circuit board formed by laminating a plurality of semiconductor element built-in type boards each comprising an insulating substrate and a semiconductor element accommodated in a recess formed therein, characterized in that a difference between a linear expansion coefficient of the insulating substrate and a linear expansion coefficient of the semiconType: GrantFiled: September 29, 2006Date of Patent: March 5, 2013Assignees: Ibiden Co., Ltd., National University Corporation Tohoku UniversityInventors: Ryo Enomoto, Tadahiro Ohmi, Akihiro Morimoto
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Patent number: 8384842Abstract: A display device which narrows a width of a frame thereof is provided. A display device includes a first substrate on which a plurality of switching elements is formed, a second substrate which is arranged to face the first substrate in an opposed manner, and a frame which is mounted on an outer peripheral portion of the first substrate by way of an adhesive layer. The adhesive layer and the frame each have an opening at a position corresponding to the plurality of switching elements formed on the first substrate, and an inner peripheral surface of the opening of the frame and an inner peripheral surface of the opening of the adhesive layer are made coplanar with each other.Type: GrantFiled: July 29, 2009Date of Patent: February 26, 2013Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Atsuo Nakagawa, Eiji Oohira
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Patent number: 8379402Abstract: A wiring board having a lead pin is provided. The wiring board having the lead pin includes a connecting pad which is formed on the wiring board, and to which the lead pin is bonded through a conductive material. The lead pin includes: a shaft portion; a head portion which is provided on one end of the shaft portion; a protruded portion which is formed on a surface side of the head portion opposed to the connection pad; and a first taper portion which is formed between the head portion and a base part of the shaft portion.Type: GrantFiled: December 8, 2009Date of Patent: February 19, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiro Oshima, Yoshikazu Hirabayashi, Shigeo Nakajima, Yoshitaka Matsushita
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Patent number: 8351213Abstract: An electrical assembly including a substantially planar substrate having at least one recess therein and a plurality of electrical components. The electrical components are positioned in the at least one recess and include a first electrical component and a second electrical component. Each of the electrical components has a body and an electrical connection. The electrical connection of the first electrical component and the electrical connection of the second electrical component are aligned with each other when the body of the first electrical component is in a recess and the body of the second electrical component is in a recess.Type: GrantFiled: May 16, 2007Date of Patent: January 8, 2013Inventors: Brian Gorrell, Austin A. Saylor
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Patent number: 8345438Abstract: An electronic part module includes a wiring substrate, a passive device group of passive devices formed on the wiring substrate, and device chips mounted on the wiring substrate. Such an electronic part module is made in the following manner. First, a wiring substrate wafer is made, to include a plurality of electronic part module formation areas. Then, a plurality of passive devices are formed in each of the electronic part module formation areas on the wiring substrate wafer. Then, the device chips are formed on each of the electronic part module formation areas on the wiring substrate wafer. Finally, the wiring substrate wafer is divided.Type: GrantFiled: August 29, 2007Date of Patent: January 1, 2013Assignees: Fujitsu Limited, Taiyo Yuden Co., Ltd.Inventors: Xiaoyu Mi, Tsuyoshi Matsuomoto, Satoshi Ueda, Takeo Takahashi
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Patent number: 8338718Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to each other through vias formed in the insulating layers. In the peripheral region around the chip mounting area of the outermost insulating layer on one of both surfaces of the board, a pad is formed in a bump shape to cover a surface of a portion of the outermost insulating layer, the portion being formed to protrude, and a pad whose surface is exposed from the insulating layer is arranged in the chip mounting area. A chip is flip-chip bonded to the pad of the package, and another package is bonded to the bump shaped pad in a peripheral region around the chip (package-on-package bonding).Type: GrantFiled: December 7, 2009Date of Patent: December 25, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kentaro Kaneko, Hidemi Atobe
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Patent number: 8339803Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.Type: GrantFiled: December 4, 2009Date of Patent: December 25, 2012Assignee: International Business Machine CorporationInventors: Wiren Dale Becker, Jinwoo Choi, Tingdong Zhou
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Patent number: 8330047Abstract: A first insulating layer is formed on a suspension body and a wiring trace is formed on the first insulating layer. In addition, a ground trace is formed on the first insulating layer so as to extend along the wiring trace on one side of the wiring trace with a spacing therebetween. A second insulating layer is formed on the first insulating layer to cover the wiring trace and the ground trace. On the second insulating layer, a wiring trace is formed at a position above the wiring trace. A third insulating layer is formed on the second insulating layer to cover the wiring trace. The width of the wiring trace is set larger than the width of the wiring trace. At least a partial region of the ground trace and at least a partial region of the wiring trace are opposite to each other with part of the second insulating layer sandwiched therebetween.Type: GrantFiled: March 24, 2009Date of Patent: December 11, 2012Assignee: Nitto Denko CorporationInventors: Voonyee Ho, Katsutoshi Kamei
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Patent number: 8325459Abstract: A first via and a second via pass through a layer of a multi-layered circuit board. A first set of electrical transmission line segments, each having a first thickness, is aligned at a first area on the layer between the first and second vias. A second set of electrical transmission line segments, each having a second thickness that is greater than the first thickness, are aligned at a second area that is offset to the first area and to the first and second vias. The first set of electrical transmission line segments is connected to the second set of electrical transmission line segments to form an electrical transmission line, which has an average impedance that matches a line impedance of a uniform thickness line.Type: GrantFiled: December 8, 2009Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Bhyrav M. Mutnury, Terence Rodrigues
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Patent number: 8314348Abstract: A multilayer printed wiring board includes a first interlaminar resin insulating layer, a first conductor circuit formed on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer formed on the first interlaminar resin insulating layer and the first conductor circuit, a second conductor circuit formed on the second interlaminar resin insulating layer. A via conductor can be formed in the opening portion. The opening portion of the second interlaminar resin insulating layer can expose a face of the first conductor circuit. The via conductor connects the first conductor circuit and the second conductor circuit. The via conductor includes an electroless plating film formed on inner wall face of the opening portion and includes an electrolytic plating film formed on the electroless plating film and on the exposed face of the first conductor circuit exposed by the opening portion.Type: GrantFiled: December 12, 2008Date of Patent: November 20, 2012Assignee: Ibiden Co., Ltd.Inventors: Toru Nakai, Sho Akai
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Patent number: 8310837Abstract: A circuit module is mounted with an IC that modulates and demodulates a multicarrier signal. The circuit module has a laminated board, which is provided internally with a plurality of conductive layers laminated having insulating layers in between, and an IC, which is provided with a plurality of ground terminals to be grounded. Of the plurality of conductive layers, a conductive layer provided proximate to the IC configures a ground layer electrically connected to the plurality of ground terminals.Type: GrantFiled: April 12, 2007Date of Patent: November 13, 2012Assignee: Panasonic CorporationInventors: Hiroshi Kawano, Munenori Fujimura, Takumi Naruse, Shuichiro Yamaguchi, Yoshinori Hashimoto