Patents Examined by Steven Sawyer
  • Patent number: 8068345
    Abstract: According to one embodiment, an electronic device includes a housing, a first substrate having rigidity and including a slit, contained in the housing, a part mount portion provided on the first substrate and adjacent to the slit, an electronic part mounted on the part mount portion and a second substrate having flexibility. The second substrate is stacked on an inside of the first substrate and an inside of the part mount portion, and it crosses the slit, thereby supporting the part mount portion to be displaceable with respect to the first substrate.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Takizawa, Hidenori Tanaka
  • Patent number: 8059416
    Abstract: An electromagnetic shielding device includes a metal frame mounted on a circuit board and having a looped surrounding wall configured with an inner space divided into first and second space portions by a partition wall unit. A cover is mounted fittingly into the inner space in the metal frame, and includes a dielectric cover body, and a conductive material layer attached to an outer surface of the cover body. The cover body has a looped surrounding wall extending downwardly from a periphery of a top wall and disposed in proximity to the looped surrounding wall of the metal frame such that the conductive material layer is in electrical contact with the looped surrounding wall of the metal frame. The cover cooperates with the metal frame to define first and second cavities having different depths and corresponding respectively to the first and second space portions.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: November 15, 2011
    Assignee: Universal Scientific Industrial (Shanghai) Co., Ltd.
    Inventors: Kuan-Hsing Li, Chih-Hsien Chiu
  • Patent number: 8054640
    Abstract: An electronic apparatus includes: a circuit board that is disposed inside a case that is formed by coupling first and second case halves, the circuit board being interposed between first and second boss portions; first and second conductive members that are disposed between a gap formed between the first boss portion and the circuit board; a third conductive member that is disposed between the first boss portion and the first conductive member and between the first boss portion and the second conductive member to electrically connect the first conductive member to the second conductive member; and a measurement circuit that is electrically connected to a first wiring and a second wiring, which are respectively connected to the first conductive member and the second conductive member, and measures an electrical characteristic value of at least one of the first conductive member and the second conductive member.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: November 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Monda, Minoru Mukai
  • Patent number: 8053674
    Abstract: A wired circuit board includes a wired circuit body portion having a wired circuit, an electrostatic charge removing portion conducted with the wired circuit body portion and having a semiconductive layer, and a conduction cut-off portion arranged between the wired circuit body portion and the electrostatic charge removing portion to cut off electrical conduction therebetween.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: November 8, 2011
    Assignee: Nitto Denko Corporation
    Inventors: Yasunari Ooyabu, Jun Ishii, Naohiro Terada
  • Patent number: 8035994
    Abstract: A cavity configured by electrically connecting an earth conductor formed on a multilayer dielectric substrate and on which a plurality of high frequency circuits are mounted, and a shield cover member. A waveguide aperture is formed on the earth conductor on which the high frequency circuits are mounted and is electrically coupled to the cavity, and an end-short-circuited dielectric waveguide formed in a direction of layer lamination of the multilayer dielectric substrate is connected to the waveguide aperture, and has a length approximately ¼ of an effective wavelength in the substrate of a signal wave. Spatial isolation between the high frequency circuits is ensured by an inexpensive and simple configuration using the single cavity.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: October 11, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takuya Suzuki
  • Patent number: 8031474
    Abstract: A printed circuit board assembly has plural printed circuit boards that are mechanically and electrically connected to each other with them being stacked, and a connection layer that connects the adjacent two printed circuit boards to each other is provided. The connection layer includes an insulation portion and an electric conduction portion. The insulation portion contains an insulating member and is adhered to each of the adjacent two printed circuit boards. The electric conduction portion passes through the insulation portion and connects electrode terminals of the adjacent two printed circuit boards.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventors: Minoru Ogawa, Kazuto Nishimoto
  • Patent number: 8031481
    Abstract: The present invention is provided a structure for mounting a printed board in which each connector that is attached to each of a plurality of sub printed boards, which are juxtaposed to one another with respect to a main printed board secured to a metal backboard, is inserted into each of a plurality of connectors that are juxtaposed to one another on the main printed board so that the sub printed boards are mounted on the main printed board by the connector connections. Parts of both ends of an area in proximity to a semiconductor-device mounted area on each of the sub printed boards ate pinched between a first metal frame and a second metal frame so that each of the sub printed boards are secured.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: October 4, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Shimoirisa, Atsumi Kawata, Fusaaki Kozawa
  • Patent number: 8018733
    Abstract: A circuit board interconnection system is disclosed according to the embodiments of the present invention. The system includes a first circuit board, a second circuit board, a third circuit board, a first connector and a second connector. The first connector and the second connector are mounted at two sides of the first circuit board respectively so that the second circuit board mounted on the first connector is perpendicular to the third circuit board on the second connector. The first connector and the second connector mounted respectively at two sides of the first circuit board are coupled to each other via an impedance controlled mechanism on the first circuit board. Another circuit board interconnection system, a circuit board, a connector assembly and a method for manufacturing a circuit board are disclosed according to the present invention.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: September 13, 2011
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Gongxian Jia
  • Patent number: 8014165
    Abstract: A connector for mounting to a panel is provided that includes a housing that has a front edge configured to be located proximate an opening in the panel. The connector also includes a tab that extends from the front edge of the housing where the tab is oriented to engage an outer surface of the panel. A spring member also extends from the front edge of the housing and is positioned to engage an inner surface of the panel. The spring member is flexible toward and away from the tab.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: September 6, 2011
    Assignee: Tyco Electronics Corporation
    Inventors: Richard Elof Hamner, Matthew Richard McAlonis
  • Patent number: 8003893
    Abstract: A multilayer ceramic circuit board includes ceramic wiring layers which are stacked together, one or two or more lifting layers which have a planar shape and which are disposed as an inner layer inside the stacked ceramic wiring layers or as a lower layer lower than a bottom ceramic wiring layer, and a protruding portion formed on a surface of a top ceramic wiring layer due to the disposition of the one or two or more lifting layers. The protruding portion smoothly protrudes and has a large area and high flatness. The multilayer ceramic circuit board is formed by disposing lifting layers as an inner layer of a plurality green sheets or as a lower layer lower than a bottom green sheet, and firing under pressure the resulting laminate in a state constrained by an elastic constraining sheet and a rigid constraining sheet.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: August 23, 2011
    Assignee: Alps Electric Co., Ltd.
    Inventors: Hisao Miura, Shinji Murata
  • Patent number: 7992296
    Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The method in accordance with an embodiment of the present invention includes: providing a substrate on which a first insulation layer, a first circuit pattern, a second insulation layer and a resin layer are successively laminated; boring a through-hole penetrating the substrate; forming roughness on the resin layer by a desmear process; forming a via making an electrical connection between layers through the through-hole; and forming a second circuit pattern on the resin layer having roughness formed thereon.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: August 9, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woon-Chun Kim, Sung Yi
  • Patent number: 7987589
    Abstract: A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: August 2, 2011
    Assignee: Unimicron Technology Corp.
    Inventors: Han-Pei Huang, Cheng-Hung Yu
  • Patent number: 7986495
    Abstract: A first insulating layer is formed on a suspension body, and a write wiring trace and a read wiring trace are formed on the first insulating layer. A second insulating layer is formed on the first insulating layer so as to cover the wiring traces. A write wiring trace and a read wiring trace are formed on the second insulating layer. A third insulating layer is formed on the second insulating layer so as to cover the wiring traces. The width of the wiring trace is larger than the width of the wiring trace, and the width of the wiring trace is larger than the width of the wiring trace.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: July 26, 2011
    Assignee: Nitto Denko Corporation
    Inventors: Katsutoshi Kamei, Voonyee Ho
  • Patent number: 7983052
    Abstract: The invention relates to an electronic device chassis, comprising at least an opening on the chassis and an inward guide apparatus along the opening; the guide apparatus comprises at least a first guide part and a second guide part which are respectively a concave slide and a convex slide, to guide modules in at least two different structural specifications into the electronic device to establish electrical connection with the electronic device. The module is inserted through the opening along the slides, and is fitted to the corresponding connector on the mainboard. The invention can solve the problem that traditional switch devices can not support different transmission speeds and transmission modes between networks. With the slides, a device can be compatible with data transmission modules with different speeds and different interface forms.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: July 19, 2011
    Assignee: Hangzhou Huawei-3Com Technology Co., Ltd
    Inventor: Tao Jiang
  • Patent number: 7977580
    Abstract: An intermediate multilayer wiring board product includes: a stack of a plurality of resin insulating layers, a first conductor layer, and a second conductor layer. The stack includes: a product forming region comprising a plurality of product portions arranged along a major surface of the stack, each of the plurality of product portions to become a product of the multilayer wiring board; and a frame portion surrounding the product forming region. The first conductor layer is formed on at least one of the plurality of resin insulating layers within each of the plurality of product portions. The second conductor layer is formed on at least one of the plurality of resin insulating layers within the frame portion. The frame portion has a plurality of cuts penetrating the frame portion in a thickness direction thereof, the plurality of cuts being arranged at substantially equal intervals.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: July 12, 2011
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Seigo Ueno, Toshiya Asano
  • Patent number: 7969712
    Abstract: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: June 28, 2011
    Assignee: Oracle America, Inc.
    Inventors: Leesa Noujeim, David Hockanson, Istvan Novak
  • Patent number: 7957151
    Abstract: An electrode connection structure including a first circuit component including a resin plate, a barrier film stacked on a surface of the resin plate, a circuit section formed on the barrier film and a first electrode provided on the surface of the resin plate on which the barrier film is stacked, and a second circuit component arranged to face the first circuit component and having a second electrode facing the first electrode, wherein the first and second electrodes are electrically connected via pressure applied thereto in the directions approaching each other and a portion of the barrier film surrounding the first electrode is at least partially removed from the surface of the resin plate.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: June 7, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Aita, Yoshimasa Chikama
  • Patent number: 7948758
    Abstract: The invention relates to a circuit board unit and a method for production thereof. The circuit board unit comprises a circuit board topmost laminate with conductive tracks on the upper side for mounting surface-mountable devices. The circuit board topmost laminate features a thickness dimensioned such that the anticipated heat dissipated by the surface-mountable devices is transported from the upper side to the underside of the circuit board laminate to good effect. The circuit board unit further comprises an electrically insulating laminate arranged under the circuit board topmost laminate, inserts made of a material with good heat conductivity and electrical insulation embedded in the electrically insulating laminate at sites below surface-mountable devices with high heat dissipation, and a cooling plate arranged below the electrically insulating laminate and the inserts.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: May 24, 2011
    Assignees: Agie Charmilles SA, Charmilles Technologies SA
    Inventors: Ernst Bühler, Rino D'Amario, Reto Knaak
  • Patent number: 7948761
    Abstract: The present invention provides a technique which can decrease the number of folding times of a flexible printed circuit board in a display device having the structure which can fold the flexible printed circuit board in a compact form by folding the flexible printed circuit board plural times. The display device includes a display panel having substrates, and a flexible printed circuit board having one end thereof fixed to a peripheral portion of a first side of the substrate, wherein the flexible printed circuit board forms an I/F portion on which a plurality of input terminals is formed in the inside thereof in a state that the flexible printed circuit board is developed.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: May 24, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventor: Fumiaki Komori
  • Patent number: 7935893
    Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 3, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita