Patents Examined by Steven T Sawyer
  • Patent number: 11930596
    Abstract: Described herein are dielectric polymer films and printed circuit boards, such as multilayer and high-density interconnect printed circuit board comprising at least one dielectric polymer film.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: March 12, 2024
    Assignee: Thintronics, Inc.
    Inventors: Tarun Amla, Stefan J. Pastine
  • Patent number: 11923284
    Abstract: A wiring substrate that is provided enables stray capacitance between a first electrode and a second electrode to be prevented from varying when an undulation occurs in the wiring substrate. Insulating layers are stacked. A first electrode and a second electrode are formed between the same layers at an interval. The thickness of the first electrode is more than the thickness of the second electrode. The lower main surface of the first electrode is located at a position lower than the lower main surface of the second electrode, and the upper main surface of the first electrode is located at a position higher than the upper main surface of the second electrode when seen through in a direction perpendicular to a stacking direction of the insulating layers.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 5, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryota Asai, Issei Yamamoto
  • Patent number: 11924968
    Abstract: The laminate of the present disclosure is a laminate including multiple glass ceramic layers each containing quartz and a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal. An Al2O3 content of a surface layer portion of the laminate is higher than an Al2O3 content of an inner layer portion of the laminate, and a M2O content of the surface layer portion is lower than a M2O content of the inner layer portion.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 5, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka Senshu, Yasutaka Sugimoto, Sadaaki Sakamoto
  • Patent number: 11915840
    Abstract: A cable includes a first conductor and a first conductor isolation, wherein the first conductor includes at least a first break point between the first and second end of the cable and the first conductor isolation includes at least a second break point between the first and second end of the cable, the cable is configured so that the first conductor breaks at the at least first break point if the cable is exposed to a force that is above a first predetermined limit and first conductor isolation breaks at the at least second break point if the cable is exposed to a force that is above a second predetermined limit for avoiding hazardous electric shock after a crash of the vehicle.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 27, 2024
    Assignee: NINGBO GEELY AUTOMOBILE RESEARCH & DEV. CO., LTD.
    Inventor: Linus Hallberg
  • Patent number: 11917751
    Abstract: A multilayer wiring board that improves the reliability of connection at a via hole connection portion, and a method for producing the multilayer wiring board. In a multilayer wiring board comprising a plurality of metal wiring layers alternately laminated with insulating layers interposed therebetween are electrically connected to each other via a via hole plated layer, wherein a dissimilar metallic layer, made from material different from that of the metal wiring layers, is interposed between each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer, and the dissimilar metallic layer interposed between the each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer is arranged in a concave shape on the surface of the concave portion formed in the metal wiring layer on the bottom surface of the via hole.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: February 27, 2024
    Assignee: TOPPAN INC.
    Inventor: Masao Aratani
  • Patent number: 11917747
    Abstract: A circuit board module includes a circuit board, a metal core printed circuit board, and a heating element. The circuit board includes a substrate, and a surface of the substrate has an assembling region. The metal core printed circuit board is on the assembling region and includes a first circuit layer and a second circuit layer. The first circuit layer and the second circuit layer are electrically connected to each other. The second circuit layer is electrically connected to the circuit board. The thermal conductivity of the metal core printed circuit board is greater than the thermal conductivity of the substrate. The heating element is on the metal core printed circuit board and is electrically connected to the first circuit layer. An electronic device having the circuit board module is also provided.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: February 27, 2024
    Assignee: CHICONY ELECTRONICS CO., LTD.
    Inventor: Chien-Yueh Chen
  • Patent number: 11910527
    Abstract: A substrate with an electronic component embedded therein includes: a core layer having a through-portion; an electronic component disposed in the through-portion; an encapsulant disposed on a lower surface of the core layer, disposed in at least a portion of the through-portion, and covering at least a portion of a lower surface of the electronic component; and a build-up structure disposed on an upper surface of the core layer, and including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Song I Kim, Mi Sun Hwang
  • Patent number: 11889634
    Abstract: A method of manufacturing a printed circuit board includes providing an insulating layer, forming a plating seed layer on the insulating layer, forming a first circuit pattern on the plating seed layer and a second circuit pattern on the first circuit pattern, and forming a top metal layer on the second circuit pattern. The second circuit pattern can be thinner than the first circuit pattern, and the top metal layer can be wider than the second circuit pattern.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 30, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jung Ho Hwang, Han Su Lee, Dae Young Choi, Soon Gyu Kwon, Dong Hun Jeong, In Ho Jeong, Kil Dong Son, Sang Hwa Kim, Sang Young Lee, Jae Hoon Jeon, Jin Hak Lee, Yun Mi Bae
  • Patent number: 11882652
    Abstract: The present disclosure relates to a printed circuit board. The printed circuit board includes: a plurality of insulating layers; a plurality of circuit layers disposed on at least one of an interior and an exterior of the plurality of insulating layers; and a reinforcing layer disposed on one surface of the plurality of insulating layers, and having a first opening having a first width and a second opening having a second width, different from the first width.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 23, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Je Ji, Seung Eun Lee, Yong Hoon Kim
  • Patent number: 11882655
    Abstract: A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 23, 2024
    Assignee: DELL PRODUCTS L.P.
    Inventors: Umesh Chandra, Douglas Wallace, Bhyrav Mutnury
  • Patent number: 11882658
    Abstract: A printed circuit board system includes a plurality of printed circuit board (PCB) assemblies that includes at least three PCB assemblies and a connecting module. The connecting module is coupled to each of the PCB assemblies. The connecting module is adapted to provide electrical and signal communications between each of the PCB assemblies. The connecting module is on different planes with respect to at least one of the PCB assemblies.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 23, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yaw-Tzorng Tsorng, Tung-Hsien Wu, Wei-Jie Chen
  • Patent number: 11877395
    Abstract: Provided is a thermoplastic liquid crystal polymer film (TLCP film) having a dielectric constant in a thickness direction of the film, which is suitable for a millimeter-wave radar substrate. The TLCP film is a film comprising a thermoplastic polymer capable of forming an optically anisotropic melt phase, wherein the TLCP film has a dielectric constant of from 2.5 to 3.2 in the thickness direction of the film at a temperature of 23° C. and a frequency of 20 GHz, and a heat deformation temperature of from 180 to 320° C. The TLCP film has, on a film plane, dielectric constants of from 2.6 to 3.7 at a temperature of 23° C. and a frequency of 15 GHz both in one direction of the film and in a direction perpendicular to the one direction of the film.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 16, 2024
    Assignee: KURARAY CO., LTD.
    Inventors: Minoru Onodera, Tatsuya Sunamoto, Takeshi Takahashi, Takahiro Nakashima
  • Patent number: 11871516
    Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An electronic apparatus is provided. The electronic apparatus includes a printed circuit board (PCB), an antenna module mounted on a surface of the printed circuit board, and a radio frequency integrated circuit (RFIC) module mounted on another surface of the printed circuit. The printed circuit board includes a coaxial plated through-hole (PTH) electrically connected with the antenna module and the RFIC.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: January 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanghyun Baek, Juneseok Lee, Dohyuk Ha, Youngju Lee, Jinsu Heo
  • Patent number: 11871525
    Abstract: A wiring board according to the present disclosure has at least a structure in which a wiring conductor layer is layered on a surface of an insulating layer containing particles of silica, and some particles of silica among the particles of silica contained in the insulating layer are partially exposed on the surface of the insulating layer. The wiring conductor layer includes a seed layer in contact with the insulating layer and a plated conductor layer formed on a surface of the seed layer. At a contact surface between the exposed portions of the particles of silica and the seed layer, an amorphous layer of silica derived from the particles of silica and an amorphous layer of metal derived from metal forming the seed layer are present.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 9, 2024
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshihiro Hasegawa
  • Patent number: 11864313
    Abstract: A multilayer wiring substrate according to the present invention includes a dielectric base body, a signal line in or on the dielectric base body, a ground conductor in the dielectric base body, and a graphite sheet in the dielectric base body. The dielectric base body is a laminate including dielectric sheets stacked on top of each other. The ground conductor and the signal line face each other in a stacking direction of the dielectric sheets. The ground conductor overlaps the signal line when viewed in plan in the stacking direction. The graphite sheet and the signal line face each other in the stacking direction without the signal line being located between the graphite sheet and the ground conductor. An upper surface of the graphite sheet is coplanar with an upper surface of the ground conductor or is located below the upper surface of the ground conductor.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: January 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kishimoto, Masatoshi Kakue, Shuichi Kawata, Hiroshi Nishikawa
  • Patent number: 11864307
    Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Jung Byun, Jung Soo Kim, Sang Hyun Sim, Chang Min Ha, Tae Hong Min, Jin Won Lee
  • Patent number: 11864327
    Abstract: An inductor structure is provided that is positioned within a via of a printed circuit board. The inductor structure includes a via extending through a printed circuit board. The inductor structure includes at least one coil of an electrically conductive material beginning at a first opening to the via continuously present on a sidewall of the via encircling a center of the via extending to a second opening of the via opposite the first opening of the via. It further includes at least electrode present in contact with an end of the coil at said first or second opening.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 2, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Bartley, Darryl Becker, Matthew Doyle, Mark Jeanson
  • Patent number: 11844178
    Abstract: An electronic device and a method of forming such an electronic device are disclosed. The electronic device can include an integrated device package and a component. The integrated device package includes a substrate and a package body over the substrate, and a hole formed through the package body to expose a conductive pad of the substrate. The component is mounted over the package body, and includes a component body and a lead extending from the component body through the hole. The lead includes an insulated portion and a distal exposed portion, and the insulated portion includes a conductor and an insulating layer disposed about the conductor, wherein the distal exposed portion is uncovered by the insulating layer such that the conductor is exposed at the distal portion. The electronic device can also include a conductive material that electrically connects the distal exposed portion to the conductive pad of the substrate.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: December 12, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: John David Brazzle, Sok Mun Chew
  • Patent number: 11837641
    Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
  • Patent number: 11826169
    Abstract: A mouth guard senses impact forces and determines if the forces exceed an impact threshold. If so, the mouth guard notifies the user of the risk for injury by haptic feedback, vibratory feedback, and/or audible feedback. The mouth guard system may also remotely communicate the status of risk and the potential injury. The mouth guard uses a local memory device to store impact thresholds based on personal biometric information obtained from the user and compares the sensed forces relative to those threshold values. The mouth guard and its electrical components on the printed circuit board are custom manufactured for the user such that the mouth guard provides a comfortable and reliable fit, while ensuring exceptional performance.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: November 28, 2023
    Assignee: Force Impact Technologies, Inc.
    Inventors: Anthony M. Gonzales, Robert M. Merriman, Susan M. Merriman, Christopher T. Cooper