Patents Examined by Steven T Sawyer
  • Patent number: 11330701
    Abstract: A module board of an embodiment includes a printed board having a through-hole, a semiconductor device mounted on the printed board so as to cover the through-hole, and a heat conductive polygonal column included in the through-hole. The semiconductor device includes a ground terminal or a power supply terminal, the polygonal column is supported by the through-hole at the corners of the polygonal column, and the polygonal column is connected to the ground terminal or the power supply terminal.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: May 10, 2022
    Assignee: Kioxia Corporation
    Inventor: Katsuya Murakami
  • Patent number: 11322456
    Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Venkata Suresh R. Guthikonda, Shankar Devasenathipathy, Chandra M. Jha, Je-Young Chang, Kyle Yazzie, Prasanna Raghavan, Pramod Malatkar
  • Patent number: 11324115
    Abstract: A circuit board includes a wiring board. The wiring board includes a first wiring layer, a dielectric layer and a second wiring layer stacked, and a plurality of spaced conductive pillars. Each conductive pillar connects the first wiring layer and the second wiring layer. A groove is recessed from a side of the dielectric layer facing away from the second wiring layer, and includes first recessed portion and at least two spaced second recessed portions recessed from a sidewall of the first recessed portion. An end surface of each conductive pillar is exposed from the at least two spaced second recessed portions, and a sidewall of each pillar close to the first recessed portion is exposed from the second recessed portion. At least one electronic component is received in the first recessed portion, and is connected to the conductive pillars through electrical connecting portions received in the second recessed portions.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 3, 2022
    Assignees: QING DiNG PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited., GARUDA TECHNOLOGY CO., LTD
    Inventor: Yong-Chao Wei
  • Patent number: 11312319
    Abstract: A wire harness includes a plurality of insulated electric wires, a sheath covering a part in a longitudinal direction of the insulated wires, and a branching portion fixing member covering an end portion of the sheath with the insulated wires guided out therefrom, and one-parts in respective longitudinal directions of the insulated wires being guided out from the end portion of the sheath. The branching portion fixing member includes a plurality of guiding-out portions to guide out the one-parts of the plurality of insulated wires respectively. The wire harness is provided with a protective tube to cover at least one of the guiding-out portions, and the insulated wire guided out from the at least one of the guiding-out portions, and a tightening member to tighten and fix one end portion of the protective tube to an outer peripheral surface of the at least one of the guiding-out portions.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: April 26, 2022
    Assignee: HITACHI METALS, LTD.
    Inventors: Hirotaka Eshima, Takahiro Futatsumori
  • Patent number: 11317511
    Abstract: The present disclosure provides a circuit board. The circuit board may include a number of stacked core boards each having a top surface. At least part core boards of the number of stacked core boards may include circuit layers at top surfaces thereof. A groove may be defined through the at least part core boards. A conductive material may be received in the groove configured to couple to the circuit layers of at least two core boards. A cross section of the groove may include a length in a first direction and a length in a second direction, and the length in the first direction may be greater than the length in the second direction. Electroplating solution may capable of contacting any portions of the groove to electroplate, to form the conductive material.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: April 26, 2022
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Zhi Li, Xuechuan Han, Rong Cui, Zhenbo Liu
  • Patent number: 11315844
    Abstract: A substrate has a first surface and a second surface opposite to the first surface. The substrate has at least one first recess on the first surface and a second recess on the second surface. The substrate includes electrode pads. The electrode pads are in the at least one first recess. The substrate has the at least one first recess located separate from the second recess in a plan view.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 26, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Fumiaki Takeshita, Teruaki Nonoyama
  • Patent number: 11310914
    Abstract: A circuit board includes a board body, a first electrode, and a second electrode. The board body contains a resin material. The first electrode is disposed on a first main surface of the board body and includes a first electrode base and a first coating film that covers at least a part of an outer surface of the first electrode base. The second electrode is disposed on the first main surface of the board body and includes a pillar-shaped structure that includes a second electrode base, a first plating film that is disposed on the second electrode base, and a first plating structure having a first end directly connected to the first plating film, and a second coating film that covers at least a part of an outer surface of the pillar-shaped structure.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takafumi Kusuyama
  • Patent number: 11309478
    Abstract: This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: April 19, 2022
    Assignees: The Regents of the University of Colorado, a body corporate, The Government of the United States of America, as represented by the Secretary of Commerce National Institite of Standards and Technology
    Inventors: Donald David, David Pappas, Xian Wu
  • Patent number: 11302618
    Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Shawna M. Liff, Thomas Sounart, Johanna M. Swan
  • Patent number: 11291122
    Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian Bayraktaroglu, Roy Dittler, Ke Liu, Suddhasattwa Nad, Marcel A. Wall, Rahul N. Manepalli, Ravindra V. Tanikella
  • Patent number: 11284513
    Abstract: Various embodiments of the disclosure disclose a device including a main printed circuit board in which a band stop filter that interrupts at least some signals corresponding to a signal received from or transmitted to an antenna module is formed in via group patterns, and an antenna module connected to the main printed circuit board, and a printed circuit board. Various embodiments are possible.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungho Yoo, Namkyoung Kim, Jaeyong Ko, Youjin Kim, Tongho Chung
  • Patent number: 11277907
    Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and a partially exposed layer in a central region of the stack being exposed with regard to an upper side and a lower side by a respective blind hole formed in the stack, wherein each of opposing main surfaces of the exposed layer is partially covered by a respective adhesive layer.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: March 15, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Markus Leitgeb, Bernhard Reitmaier
  • Patent number: 11277911
    Abstract: A ceramic copper circuit board according to an embodiment includes a ceramic substrate and a first copper part. The first copper part is bonded at a first surface of the ceramic substrate via a first brazing material part. The thickness of the first copper part is 0.6 mm or more. The side surface of the first copper part includes a first sloped portion. The width of the first sloped portion is not more than 0.5 times the thickness of the first copper part. The first brazing material part includes a first jutting portion jutting from the end portion of the first sloped portion. The length of the first jutting portion is not less than 0 ?m and not more than 200 ?m. The contact angle between the first jutting portion and the first sloped portion is 65° or less.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 15, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa Kato, Takashi Sano
  • Patent number: 11272623
    Abstract: A wiring substrate includes an insulating layer having a front surface and a back surface and at least two wiring parts that are disposed at least on the front surface of the insulating layer and that are insulated from each other. At least one of the wiring parts is electrically isolated on the insulating layer. Each of the wiring parts includes a conductive base layer disposed on the front surface of the insulating layer, a conductive layer disposed on a front surface of the conductive base layer, and a conductive covering layer arranged to cover at least a portion of a front surface of the conductive layer, at least a portion of a side surface of the conductive base layer, and at least a portion of a side surface of the conductive layer. The conductive base layer and the conductive layer overlap and coincide with each other in plan view.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: March 8, 2022
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventor: Yosuke Sonohara
  • Patent number: 11272612
    Abstract: A flexible substrate includes a plurality of unit wiring structures and an insulation sheet on which the plurality of unit wiring structures are disposed. Each of the plurality of unit wiring structures includes a central section and a plurality of strips disposed at an outer side of the central section. Each of the plurality of strips has a first end and a second end, and is curved along an outer periphery of at least part of the central section, the first end connected to the central section. The plurality of strips in each of the plurality of unit wiring structures curve in a clockwise or a counterclockwise manner with the central section as a center of rotation. The plurality of unit wiring structures include at least four unit wiring structures arranged in a two-dimensional manner.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 8, 2022
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yoshihiro Tomita
  • Patent number: 11266008
    Abstract: An electrical assembly includes an electrical connector mounted upon a PCB and receiving a CPU therein, and a liquid Nitrogen heat dissipation device is mounted upon the PCB and intimately seated upon the CPU to remove the heat therefrom. The liquid Nitrogen heat dissipation device includes a case forming a chamber to receive the liquid Nitrogen therein. A plurality of fixing arms extend outwardly and radially to fix the liquid Nitrogent heat dissipation device in position. A fixing seat is attached upon the PCB to precisely located the CPU in position with regard to the electrical connector.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 1, 2022
    Assignees: FUDING PRECISION COMPONENTS (SHENZHEN) CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Heng-Kang Wu, Xiong Tan, Fu-Jin Peng
  • Patent number: 11264737
    Abstract: A component carrier is illustrated and described. The component carrier has i) a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and ii) at least one elastic element attached to the stack and configured to reversibly connect the component carrier with a further component carrier by elastically deforming the at least one elastic element and essentially not deforming the stack and the further component carrier.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 1, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Christian Vockenberger, Rainer Frauwallner, Thomas Krivec
  • Patent number: 11257623
    Abstract: A multilayer electronic component includes: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode including an electrode layer disposed on the body and an Sn plating layer disposed on the electrode layer. A thickness of the body is defined as Tb, a thickness of the Sn plating layer is defined as Ts, Tb is 0.22 mm or less, and Ts is 4.5 ?m or more.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyun Tae Kim, Beom Seock Oh, Tai Won Choi, Woo Soon Whang, Byoung Woo Kim, Yong Won Seo
  • Patent number: 11257749
    Abstract: A wiring substrate includes: a core layer having a first face, and a second face opposite to the first face; a through hole that penetrates the core layer; a first metal layer formed on an inner wall face of the through hole and formed on or above the first and second faces; a second metal layer that is formed on the first metal layer and fills the through hole, wherein the second metal layer has a first recess portion opposed to the through hole, and a second recess portion opposed to the first recess portion via the through hole; a third metal layer provided in the first recess portion; a fourth metal layer provided in the second recess portion; a fifth metal layer formed on the second metal layer and the third metal layer; and a sixth metal layer formed on the second metal layer and the fourth metal layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 22, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kazuhiro Tanaka
  • Patent number: 11257779
    Abstract: A multilayer wiring board includes a first insulating layer, a second insulating layer stacked on the first insulating layer, a via conductor inside each of the first insulating layer and the second insulating layer, and a conductive bonding layer that bonds the via conductors to each other. The first insulating layer is directly bonded to the second insulating layer, and a relationship a1>b1 is satisfied, where a1 is a maximum diameter of the bonding layer and b1 is a maximum diameter of the via conductor at an interface with the bonding layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryosuke Takada, Toshitaka Hayashi, Hiromasa Koyama