Abstract: According to one embodiment, a display device comprises a pixel circuit, an insulating layer that covers the pixel circuit and includes a first trench, a first electrode disposed on the insulating layer, an organic layer disposed on the first electrode, a second electrode disposed on the organic layer, and a first filling layer that fills at least a part of the first trench. An end portion of the first electrode is located inside the first trench and is covered with the first filling layer.

Abstract: Light detecting structures comprising a Si base having a pyramidal shape with a wide incoming light-facing pyramid bottom and a narrower pyramid top and a Ge photodiode formed on the Si pyramid top, wherein the Ge photodiode is operable to detect light in the short wavelength infrared range, and methods for forming such structures. A light detecting structure as above may be repeated spatially and fabricated in the form of a focal plane array of Ge photodetectors on silicon.

Abstract: A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.

Abstract: In a processing method for a wafer with a mark formed in an outer peripheral portion thereof, a frame unit having the wafer, a tape, and a ring frame is provided, a set of processing conditions for processing the wafer is selected, and a representative image associated with the set of processing conditions is displayed on a display unit. The ring frame includes a notch formed in an outer periphery thereof. In the frame unit, the mark and the notch are in a positional relationship set in accordance with the set of processing conditions. The positional relationship is presented in the representative image.

Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

Abstract: The present invention discloses a novel silicon carbide-based lateral PN junction extreme ultraviolet detector with enhanced detection performance based on selective-area ion implantation, including an N-type ohmic contact lower electrode, an N-type substrate and a lightly-doped epitaxial layer which are connected sequentially from bottom to top, where the lightly-doped epitaxial layer is an N-type lightly-doped epitaxial layer or a P-type lightly-doped epitaxial layer; in a case that the lightly-doped epitaxial layer is an N-type or P-type lightly-doped epitaxial layer, a P-type or N-type well region is formed on the surface of the N-type or P-type lightly-doped epitaxial layer through the selective-area ion implantation, a P-type or N-type ohmic contact upper electrode is arranged on the P-type or N-type well region, and the P-type or N-type ohmic contact upper electrode is provided with a metal conductive electrode along its periphery.

Abstract: A light shielding structure of an optical circuit of the present invention uses a part of the structure of the light reception element itself to suppress stray light. A stepped electrode that covers an upper surface and side surface of a first semiconductor layer constituting a light absorption portion of the light reception element is formed at a height substantially equal to that of an optical waveguide in the optical circuit, and the light absorption portion of the light reception element is shielded from stray light by a wall-shaped or column-shaped wiring electrode extending substantially perpendicularly to a surface layer of the optical circuit. The light shielding structure of the present invention uses a part of the configuration of the light reception element, is formed integrally with the light reception element, and also has an aspect of the invention of the light reception element.

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.

Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.

Abstract: A method of manufacturing a semiconductor device includes forming a seed layer containing a predetermined element on a substrate by performing a process a predetermined number of times, and supplying a second precursor containing the predetermined element and not containing the ligand to the substrate to form a film containing the predetermined element on the seed layer. The process includes alternately performing: supplying a first precursor to the substrate to form an adsorption layer of the first precursor, the first precursor containing the predetermined element and a ligand which is coordinated to the predetermined element and which contains at least one of carbon or nitrogen, and supplying a ligand desorption material to the substrate to desorb the ligand from the adsorption layer of the first precursor.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

Abstract: A method for producing a composite silicon carbide structure comprises: providing an initial substrate of monocrystalline silicon carbide; depositing an intermediate layer of polycrystalline silicon carbide at a temperature higher than 1000° C. on the initial substrate, the intermediate layer having a thickness greater than or equal to 1.5 microns; implanting light ionic species through the intermediate layer to form a buried brittle plane in the initial substrate, delimiting the thin layer between the buried brittle plane and the intermediate layer, and depositing an additional layer of polycrystalline silicon carbide at a temperature higher than 1000° C. on the intermediate layer, the intermediate layer and the additional layer forming a carrier substrate, and separating the buried brittle plane during the deposition of the additional layer.

Abstract: Provided is a display panel having a display region and a non-display region, and the display panel includes: a substrate; light-emitting elements disposed at a side of the substrate and located in the display region, each of light-emitting elements includes a light-emitting layer; and a light-shielding layer disposed at a side of the light-emitting elements facing away from the substrate, the light-shielding layer includes first apertures, and in a direction perpendicular to the substrate, each first aperture does not overlap with the light-emitting layer. In an embodiment, a distance between a first point on an edge of a first orthographic projection and a second point on an edge of a second orthographic projection is defined as a distance L, which satisfies L ? d × sin ? ? n 2 - sin 2 ? ? , where d denotes a distance between the light-emitting layer and the light-shielding layer, n denotes a refractive index of a functional film layer, ? denotes a visible angle and 0°<?<90°.

Abstract: In a floating gate semiconductor nanostructure biosensor and a method for manufacturing the biosensor, the nanostructure biosensor includes a substrate, an insulating layer, a nanostructure, a source electrode and a drain electrode, a floating gate and a biological sensing material. The insulating layer is formed on the substrate. The nanostructure is protruded from the insulating layer. The source electrode and the drain electrode are formed on the insulating layer and dispose the nanostructure therebetween. The floating gate has a metal pattern or a polysilicon pattern, and extends with contacting the nanostructure. The biological sensing material has a first end combined with an immobile molecule on the floating gate, and a second end combined with a bio molecule.

Abstract: Discussed is a display apparatus including a substrate having a plurality of subpixels, an insulating layer provided on the substrate, a first electrode provided on the insulating layer, a light emitting layer provided on the insulating layer and the first electrode, and a second electrode provided on the light emitting layer. The substrate can include a left portion including one edge, a right portion including another edge, and a central portion interposed between the left portion and the right portion. Further, a first fence and a second fence are provided on the insulating layer between adjacent subpixels, a gap is inside the light emitting layer between adjacent subpixels, a trench is provided in the insulating layer between the first fence and the second fence, and the gap overlaps the trench.

Abstract: A display device may include: a substrate including a display area and a non-display area; and pixels disposed on the display area, and each including sub-pixels, each sub-pixel including a pixel circuit layer, and a display element layer including a light emitting element. The display element layer includes first and second electrodes spaced apart from each other; a first insulating layer disposed between the pixel circuit layer and the light emitting element; and a second insulating layer disposed on the light emitting element and filling spaces between the first insulating layer and ends of the light emitting element. The light emitting element includes a first conductive semiconductor layer, an active layer enclosing at least one side of the first conductive semiconductor layer, a second conductive semiconductor layer enclosing the active layer, an electrode layer enclosing the second conductive semiconductor layer, and an insulating film covering the electrode layer.

Abstract: Phosphor-converted LED side reflectors disclosed herein comprise pigments that are photochemically stable under illumination by light from the pcLED. The pigments absorb light in at least a portion of the spectrum of light emitted by the first phosphor converted LED. The side reflector may also comprise light scattering particles or air voids. The pigments, light scattering particles, or air voids may be homogeneously distributed in the reflector. Alternatively the side reflector may be layered, with the pigments, light scattering particles, or air voids inhomogeneously distributed in the reflector. The side reflector can include phosphor particles.

Abstract: A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p??-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p??-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p??-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.

Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.