Patents Examined by Sun Mi Kim King
  • Patent number: 11393902
    Abstract: A semiconductor device includes a semiconductor substrate comprising an upper surface and a lower surface, an upper electrode provided on the upper surface, and a lower electrode provided on the lower surface. The semiconductor substrate includes, in a planar view, a first section including a center of the semiconductor substrate and a second section located between the first section and a peripheral edge of the semiconductor substrate. The first and second sections each comprise a MOSFET structure including a body diode. The MOSFET structure in the first section and the MOSFET structure in the second section are different from each other such that a forward voltage drop of the body diode in the first section with respect to a current density is higher than a forward voltage drop of the body diode in the second section with respect to the current density.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 19, 2022
    Assignee: DENSO CORPORATION
    Inventors: Tatsuji Nagaoka, Yusuke Yamashita, Yasushi Urakami
  • Patent number: 11393838
    Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shibun Tsuda, Tomohiro Yamashita
  • Patent number: 11393859
    Abstract: An image sensor package including an image sensor chip including an active pixel sensor region and a non-sensing region, a plurality of chip pads being in the non-sensing region; a printed circuit board on one side of the image sensor chip, the printed circuit board including a plurality of bonding pads; conductive wires respectively connecting the plurality of chip pads to the plurality of bonding pads; a bonding dam at a periphery of the active pixel sensor region; a cover glass on the bonding dam and facing another side of the image sensor chip; and an encapsulation layer covering a side surface of the bonding dam, a side surface of the cover glass, an edge of a lower surface of the cover glass, the non-sensing region, and an edge of an upper surface of the printed circuit board, wherein the bonding dam is spaced apart from an end of a side surface of the image sensor chip by a distance of 80 ?m to 150 ?m has a height of 50 ?m to 150 ?m from the image sensor chip, and has a width of 160 ?m to 240 ?m.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungeun Jo, Youngshin Kwon
  • Patent number: 11380842
    Abstract: A method may include forming a via opening in a dielectric layer, depositing a first conductive layer along a bottom and a sidewall of the via opening, depositing a second conductive layer on top of the first conductive layer. The method may further include recessing the first conductive layer to form a trench and exposing a sidewall of the second conductive layer, depositing a non-conductive material in the trench, and depositing a phase change material layer on top of the dielectric layer. The top surface of the second conductive layer may be in direct contact with a bottom surface of the phase change material layer.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 5, 2022
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Junli Wang
  • Patent number: 11374037
    Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 28, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Satoshi Horiuchi, Yoshihiro Asai, Isao Ogasawara, Masakatsu Tominaga, Yoshihito Hara
  • Patent number: 11348893
    Abstract: A semiconductor package includes a first semiconductor die, a first substrate, a second semiconductor die, and a second substrate. The first substrate is disposed on the first semiconductor die and includes a plurality of first metal line layers vertically spaced apart from each other, and each of the first metal line layers is electrically connected to one of the followings: a ground source and a plurality of power sources of different types. The second semiconductor die is disposed on the first substrate. The second substrate is disposed on the second semiconductor die and includes a plurality of second metal line layers vertically spaced apart from each other, and each of the second metal line layers is electrically connected to one of the followings: the ground source and the power sources of different types.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 31, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11345590
    Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 31, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
  • Patent number: 11329152
    Abstract: A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: May 10, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroaki Sekikawa, Takahiro Mori, Yuji Ishii
  • Patent number: 11315933
    Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Kuo-Hsiu Hsu, Jyun-Yu Tian, Wan-Yao Wu, Chang-Yun Chang, Hung-Kai Chen, Lien Jung Hung
  • Patent number: 11316119
    Abstract: Disclosed are a curved display apparatus and a method of manufacturing the same, which improve a luminance difference between a flat part and a curved part. The curved display apparatus having a flat part and a bending part extending from one side of the flat part, either of the flat part and the bending part defining a plurality of emission areas therein, wherein the curved display apparatus comprises: a light emitting device layer including a plurality of light emitting devices to form the emission areas, wherein a slope film is provided in the bending part such that an emission surface of the emission areas in the bending part is almost parallel to an emission surface of the emission areas in the flat part.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: April 26, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Hyuck Choi
  • Patent number: 11296121
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 5, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 11289499
    Abstract: A memory device may include first and second pillar-shaped active regions formed on a substrate and extending upward. The first and second active regions are arranged in a first array and a second array, respectively. Each of the first active regions comprises alternatively stacked source/drain layers and channel layers, wherein the channel layers of the respective first active regions at a corresponding level are substantially coplanar with each other, and the source/drain layers of the respective first active regions at a corresponding level are substantially coplanar with each other. Each of the second active regions comprises an active semiconductor layer extending integrally. The memory device may include multiple layers of first storage gate stacks surrounding peripheries of and being substantially coplanar with the respective levels of the channel layers, and multiple layers of second storage gate stacks which surround peripheries of the respective second active regions.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 29, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11282706
    Abstract: A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 22, 2022
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Wagenleitner, Thomas Plach, Jurgen Markus Suss
  • Patent number: 11271184
    Abstract: The present disclosure provides an OLED package structure, OLED device, display device and method for fabricating OLED package structure. The OLED package structure includes a substrate, a cover plate and a first sealant layer. The substrate, the cover plate and the first sealant layer together delimiting a sealed space. The OLED package structure further includes a functional sealant layer formed by filling the sealed space with a functional sealant, and a second sealant layer formed by a second sealant disposed between the substrate and the functional sealant layer. The second sealant has a density less than a density of the functional sealant.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 8, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Donghui Yu, Wenjun Hou
  • Patent number: 11264503
    Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 11264485
    Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Ding-Kang Shih, Chun-Hsiung Lin, Teng-Chun Tsai, Zhi-Chang Lin, Akira Mineji, Yao-Sheng Huang
  • Patent number: 11251187
    Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 15, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng
  • Patent number: 11251273
    Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 15, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Jian-Ting Chen, Yao-Ting Tsai, Jung-Ho Chang, Hsiu-Han Liao
  • Patent number: 11211450
    Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hyun Park, Kye-hyun Baek, Yong-ho Jeon, Cheol Kim, Sung-il Park, Yun-il Lee, Hyung-suk Lee
  • Patent number: 11177127
    Abstract: Described herein are functionalized cyclosilazane precursor compounds and compositions and methods comprising same to deposit a silicon-containing film such as, without limitation, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or carbon-doped silicon oxide via a thermal atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) process, or a combination thereof.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: November 16, 2021
    Assignee: Versum Materials US, LLC
    Inventors: Manchao Xiao, Matthew R. MacDonald