Patents Examined by Sun Mi Kim King
  • Patent number: 11024742
    Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Yasutaka Nakazawa, Yukinori Shima
  • Patent number: 11018172
    Abstract: The present disclosure relates to a solid-state imaging element configured to inhibit an adverse effect, which is attributable to a light shielding film formed for disposing an OPB region, on the formation of a constituent other than the light shielding film of the solid-state imaging element, and an electronic device. According to a first aspect of the present disclosure, there is provided a solid-state imaging element, including: an effective pixel region in which a large number of pixels are vertically and horizontally arranged; and an OPB region formed by coating pixels around the effective pixel region with a light shielding film. Corners on at least one of an outer circumferential side and an inner circumferential side of the OPB region are formed into an arc shape. The present disclosure can be applied to, for example, a back-surface irradiation type CMOS image sensor.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: May 25, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takuya Nakano
  • Patent number: 10991689
    Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: April 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Abu Naser M. Zainuddin, Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala S Haran
  • Patent number: 10985112
    Abstract: A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventor: Dae-Sung Eom
  • Patent number: 10978537
    Abstract: An organic light emitting diode display includes a substrate, a plurality of pixels disposed on the substrate, a plurality of transmissive windows spaced apart from the pixels, and a light blocking member disposed between one of the pixels and one of the transmissive windows. The pixels display an image, and light is transmitted through the transmissive windows. Each pixel includes a transistor including a plurality of electrode members disposed in different layers on the substrate. The light blocking member includes a plurality of light blocking sub-members respectively disposed in the same layers as the plurality of electrode members.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kohei Ebisuno, Yong Ho Yang, Jun Hee Lee, Nak Cho Choi
  • Patent number: 10971662
    Abstract: A light-emitting diode (LED) package includes a light-emitting structure, a transmissive material layer on the light-emitting structure, and a support structure covering at least a portion of a side surface of the transmissive material layer, a side surface of the light-emitting structure, and at least a portion of a bottom surface of the light-emitting structure.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk-jin Cho, Dong-hoon Lee
  • Patent number: 10957633
    Abstract: A unit lead frame includes a periphery structure, a die paddle inside of the periphery structure, a plurality of leads extending between the periphery structure and the die paddle, and trenches or grooves extending from an outer surface of the periphery structure and configured to guide liquefied molding material onto the periphery structure along sidewalls of the trenches or grooves.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Boon Teik Tee, Tiam Sen Ong
  • Patent number: 10950710
    Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Tsai, Kei-Wei Chen
  • Patent number: 10950604
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: March 16, 2021
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Choi Kim, Chang Wook Jeong
  • Patent number: 10937863
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10930792
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10923614
    Abstract: A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p? type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p? type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p? type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p? type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p? type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Sakata, Manabu Usuda, Mitsuyoshi Mori, Yutaka Hirose, Yoshihisa Kato
  • Patent number: 10910481
    Abstract: A semiconductor device includes a semiconductor body and an insulated gate contact on a surface of the semiconductor body over an active channel in the semiconductor device. The insulated gate contact includes a channel mobility enhancement layer on the surface of the semiconductor body, a diffusion barrier layer over the channel mobility enhancement layer, and a dielectric layer over the diffusion barrier layer. By using the channel mobility enhancement layer in the insulated gate contact, the mobility of the semiconductor device is improved. Further, by using the diffusion barrier layer, the integrity of the gate oxide is retained, resulting in a robust semiconductor device with a low on-state resistance.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: February 2, 2021
    Assignee: Cree, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Lin Cheng, John Williams Palmour
  • Patent number: 10910214
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate that includes a surface exposing a first film containing silicon, oxygen, carbon and nitrogen and having an oxygen atom concentration higher than a silicon atom concentration, which is higher than a carbon atom concentration, which is equal to or higher than a nitrogen atom concentration; and changing a composition of a surface of the first film so that the nitrogen atom concentration becomes higher than the carbon atom concentration on the surface of the first film, by supplying a plasma-excited nitrogen-containing gas to the surface of the first film.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 2, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Masanori Nakayama, Masaya Nagato, Tatsuru Matsuoka, Hiroki Tamashita, Takafumi Nitta, Satoshi Shimamoto
  • Patent number: 10908499
    Abstract: This disclosure is directed to two-dimensional conformal optically-fed phased arrays and methods for manufacturing the same. The method includes providing a wafer substrate, depositing a first cladding layer on the wafer substrate, and depositing a core layer on the first cladding layer. The method further includes photolithographically patterning the core layer to provide a plurality of optical waveguide cores, and depositing a second cladding layer on the core layer to cover the plurality of optical waveguide cores to provide a plurality of optical waveguides. In addition, the method includes forming a plurality of antennas on the second cladding layer, each antenna of the plurality of antennas located near a termination of a corresponding optical waveguide of the plurality of optical waveguides, and providing a plurality of photodiodes on the second cladding layer, each photodiode of the plurality of photodiodes connected to a corresponding antenna.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 2, 2021
    Assignee: Phase Sensitive Innovations, Inc.
    Inventors: Shouyuan Shi, Dennis Prather, Peng Yao, Janusz Murakowski
  • Patent number: 10886405
    Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 5, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Hsiang Chen, Yao-Wen Chang, Chu-Yung Liu, I-Chen Yang, Hsin-Wen Chang
  • Patent number: 10870576
    Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 22, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
  • Patent number: 10868144
    Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 15, 2020
    Inventors: Runling Li, Haifeng Zhou
  • Patent number: 10818668
    Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 10818703
    Abstract: A method for manufacturing a semiconductor device includes: forming a photocatalytic layer and an organic compound layer in contact with the photocatalytic layer over a substrate having a light transmitting property; forming an element forming layer over the substrate having the light transmitting property with the photocatalytic layer and the organic compound layer in contact with the photocatalytic layer interposed therebetween; and separating the element forming layer from the substrate having the light transmitting property after the photocatalytic layer is irradiated with light through the substrate having the light transmitting property.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: October 27, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masafumi Morisue, Yasuhiro Jinbo, Gen Fujii, Hajime Kimura