Patents Examined by Sun Mi Kim King
  • Patent number: 11264503
    Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 11264485
    Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Ding-Kang Shih, Chun-Hsiung Lin, Teng-Chun Tsai, Zhi-Chang Lin, Akira Mineji, Yao-Sheng Huang
  • Patent number: 11251187
    Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 15, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng
  • Patent number: 11251273
    Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 15, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Jian-Ting Chen, Yao-Ting Tsai, Jung-Ho Chang, Hsiu-Han Liao
  • Patent number: 11211450
    Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hyun Park, Kye-hyun Baek, Yong-ho Jeon, Cheol Kim, Sung-il Park, Yun-il Lee, Hyung-suk Lee
  • Patent number: 11177127
    Abstract: Described herein are functionalized cyclosilazane precursor compounds and compositions and methods comprising same to deposit a silicon-containing film such as, without limitation, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or carbon-doped silicon oxide via a thermal atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) process, or a combination thereof.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: November 16, 2021
    Assignee: Versum Materials US, LLC
    Inventors: Manchao Xiao, Matthew R. MacDonald
  • Patent number: 11164880
    Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 2, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chih-Hsin Chen, Wei-Ren Chen
  • Patent number: 11127777
    Abstract: A first region includes first transfer column regions distributed in a first direction. A second region includes second transfer column regions distributed in the first direction. The second region is positioned downstream of the first region in a charge transfer direction. Lengths in a second direction of the first transfer column regions are equal. Lengths in the second direction of the second transfer column regions are longer than the length of the first transfer column region, and increase as the second transfer column region is positioned downstream in the charge transfer direction. A third region is disposed to correspond to the first region and extends along the first direction. A fourth region is disposed to correspond to the second region and extends such that an interval between the fourth region and a pixel region increases in response to a change in the lengths of the second transfer column regions.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 21, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Shin-ichiro Takagi, Yasuhito Yoneta, Masaharu Muramatsu
  • Patent number: 11114332
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon nitride layer deposited by plasma deposition.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 7, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Sasha Joseph Kweskin
  • Patent number: 11101406
    Abstract: An efficient wide bandgap GaN-based LED chip based on a surface plasmon effect and a manufacturing method therefor. The efficient wide bandgap GaN-based LED chip is of a flip-chip structure, and comprises, from bottom to top in sequence, a substrate, a buffer layer, an unintentionally doped GaN layer, an n-GaN layer, a quantum well layer, an electron blocking layer, a p-GaN layer, a metallic reflecting mirror layer, a passivation layer, a p-electrode layer, an n-electrode layer; and a position of a bottom surface of the metallic reflecting mirror layer connected to a surface of the p-GaN layer is provided with a micro-nano composite metal structure. A micro metal structure comprises alternating protrusion portions and recess portions; and a nano metal structure is distributed on an interface of the micro metal structure and the p-GaN layer.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: August 24, 2021
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Huamao Huang, Hong Wang, Xiaolong Hu, Zhuobo Yang, Rulian Wen, Wei Shi
  • Patent number: 11088278
    Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Liying Jiang, Siyuranga O. Koswatta, Junli Wang
  • Patent number: 11081625
    Abstract: Packaged LEDs with phosphor films, and associated systems and methods are disclosed. A system in accordance with a particular embodiment of the disclosure includes a support member having a support member bond site, an LED carried by the support member and having an LED bond site, and a wire bond electrically connected between the support member bond site and the LED bond site. The system can further include a phosphor film carried by the LED and the support member, the phosphor film being positioned to receive light from the LED at a first wavelength and emit light at a second wavelength different than the first. The phosphor film can be positioned in direct contact with the wire bond at the LED bond site.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jonathon G. Greenwood
  • Patent number: 11056527
    Abstract: Described herein are photon counting devices comprising direct mode detectors with improved signal to noise ratios which are suitable for use in X-ray imaging devices, and other imaging devices.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: July 6, 2021
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Jinbo Cao, Jongwoo Choi, Aharon Yakimov
  • Patent number: 11024742
    Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Yasutaka Nakazawa, Yukinori Shima
  • Patent number: 11018172
    Abstract: The present disclosure relates to a solid-state imaging element configured to inhibit an adverse effect, which is attributable to a light shielding film formed for disposing an OPB region, on the formation of a constituent other than the light shielding film of the solid-state imaging element, and an electronic device. According to a first aspect of the present disclosure, there is provided a solid-state imaging element, including: an effective pixel region in which a large number of pixels are vertically and horizontally arranged; and an OPB region formed by coating pixels around the effective pixel region with a light shielding film. Corners on at least one of an outer circumferential side and an inner circumferential side of the OPB region are formed into an arc shape. The present disclosure can be applied to, for example, a back-surface irradiation type CMOS image sensor.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: May 25, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takuya Nakano
  • Patent number: 10991689
    Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: April 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Abu Naser M. Zainuddin, Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala S Haran
  • Patent number: 10985112
    Abstract: A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventor: Dae-Sung Eom
  • Patent number: 10978537
    Abstract: An organic light emitting diode display includes a substrate, a plurality of pixels disposed on the substrate, a plurality of transmissive windows spaced apart from the pixels, and a light blocking member disposed between one of the pixels and one of the transmissive windows. The pixels display an image, and light is transmitted through the transmissive windows. Each pixel includes a transistor including a plurality of electrode members disposed in different layers on the substrate. The light blocking member includes a plurality of light blocking sub-members respectively disposed in the same layers as the plurality of electrode members.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kohei Ebisuno, Yong Ho Yang, Jun Hee Lee, Nak Cho Choi
  • Patent number: 10971662
    Abstract: A light-emitting diode (LED) package includes a light-emitting structure, a transmissive material layer on the light-emitting structure, and a support structure covering at least a portion of a side surface of the transmissive material layer, a side surface of the light-emitting structure, and at least a portion of a bottom surface of the light-emitting structure.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk-jin Cho, Dong-hoon Lee
  • Patent number: 10957633
    Abstract: A unit lead frame includes a periphery structure, a die paddle inside of the periphery structure, a plurality of leads extending between the periphery structure and the die paddle, and trenches or grooves extending from an outer surface of the periphery structure and configured to guide liquefied molding material onto the periphery structure along sidewalls of the trenches or grooves.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Boon Teik Tee, Tiam Sen Ong