Abstract: The present invention relates to a method for manufacturing a membrane component with a membrane made of a thin film (<1 ?m, thin-film membrane). The membrane component can be used in microelectromechanical systems (MEMS). The invention is intended to provide a method for manufacturing a membrane component, the membrane being manufacturable with high-precision membrane dimensions and a freely selectable membrane geometry. This is achieved by a method comprising . . . providing a semiconductor wafer (100) with a first layer (116), a second layer (118) and a third layer (126). Depositing (12) a first masking layer (112) on the first layer (116), the first masking layer (112) defining a first selectively processable area (114) for determining a geometry of the membrane (M1). Forming (13) a first recess (120) by anisotropic etching (13) of the first layer (116) and removing the first masking layer (112).

Abstract: A wireless circuit includes a housing having at least one opening, and sensor connected to the housing at the opening. The sensor includes a first layer having a first dimension and a second layer having a second dimension shorter than the first dimension. The second layer may be positioned entirely within the housing and a surface of said first layer may be exposed to an exterior of the housing.

Abstract: A mechanical microsystem including a pair of elastically deformable elements, a mechanical hinge joining the deformable elements together, and at least two electroactive layers. The microsystem is configured such that, from a rest position wherein the deformable elements fall into a plane, a deformation of one of the deformable elements displacing it outside of the plane induces an electric current circulation in one of the two electroactive layers, and/or conversely. Each deformable element has a front face and a rear face opposite one another and substantially parallel to the plane. A first electroactive layer is arranged together with a first deformable element on its rear face, and a second electroactive layer, different from the first layer, is arranged with a second deformable element, different from the first element, on its front face.

Abstract: An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger and has a second height less than the first height.

Abstract: A semiconductor device includes a semiconductor chip, a substrate having a main surface on which the semiconductor chip is arranged, a resin case which has a storage space therein and a side wall, the side wall having an injection path extending from the storage space to a device exterior, the resin case having a first opening at a bottom side thereof, connecting the storage space to the device exterior, the substrate being disposed on the resin case, at a main surface side of the substrate facing at the bottom side of the resin case, and a sealing material filling the storage space and the injection path.

Abstract: Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.

Abstract: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.

Abstract: An apparatus comprising a multilevel wiring structure comprising aluminum interconnections. The aluminum interconnections comprise a first portion, a second portion, and a third portion, where the second portion is between the first portion and the third portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. A memory device comprising a memory array comprising memory cells and a control logic component electrically connected to the memory array. At least one of the memory cells comprises a multilevel wiring structure comprising interconnect structures, where the interconnect structures comprise a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. Related apparatus, memory devices, and methods are also disclosed.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.

Abstract: A sensor comprising a support and a flexible structure arranged on the support is provided. The flexible structure comprises a frustum-shaped portion having a wider end and a narrower end, wherein the wider end of the frustum-shaped portion is arranged proximal to the support, and an elongated portion extending from the narrower end of the frustum-shaped portion, wherein the flexible structure further comprises a stretchable conducting film arranged on the frustum-shaped portion. A method of preparing such a sensor is also provided.

Abstract: Methods for filling the gap of a semiconductor feature comprising exposure of a substrate surface to a precursor and reactant and an anneal environment to decrease the wet etch rate ratio of the deposited film and fill the gap.

Abstract: A radiation detector has a photoelectric conversion element array having a light receiving unit and a plurality of bonding pads; a scintillator layer stacked on the photoelectric conversion element array; a resin frame formed on the photoelectric conversion element array so as to pass between the scintillator layer and the bonding pads away from the scintillator layer and the bonding pads and so as to surround the scintillator layer; and a protection film covering the scintillator layer and having an outer edge located on the resin frame; a first distance between an inner edge of the resin frame and an outer edge of the scintillator layer is shorter than a second distance between an outer edge of the resin frame and an outer edge of the photoelectric conversion element array; the outer edge and a groove are processed with a laser beam.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active area including a channel region sandwiched between two source/drain regions; an insulation region surrounding the active area from a top view; and a dielectric layer disposed over and in contact with an interface between the insulation region and the source/drain regions. A method of manufacturing the same is also disclosed.

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.

Abstract: A production method for a micromechanical device having inclined optical windows. First and second substrates are provided. A plurality of through-holes is produced in the first and second substrate such that for each through-hole in the first substrate a congruent through-hole is produced in the second substrate, which overlap when the first substrate is placed over the second substrate. A slanted edge region is produced around a respective through-hole in the first and second substrate, the edge region being inclined at a window angle, two slanted edge regions situated on top of each other being congruent in a top view and being inclined at the same window angle. A window foil is provided having a structured window region, which covers the through-hole in a top view of the window foil in each case, the window foil forming an optical window slanted at the window angle above the respective through-hole.

Abstract: A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.