Patents Examined by Sun Mi Kim King
  • Patent number: 10332979
    Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 25, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Runling Li, Haifeng Zhou
  • Patent number: 10326025
    Abstract: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10319759
    Abstract: An image pickup element mounting substrate includes: a frame body composed of an insulating layer, a through hole being defined by an internal periphery of the frame body; an electronic component mounted on a lower surface side of the frame body; and a flat plate which is disposed on a lower surface of the frame body and covers an opening of the through hole while being partly kept in out-of-contact with the electronic component, the flat plate including an image pickup element mounting section at a part of an upper surface thereof which part is surrounded by the frame body, a lower surface of the electronic component being located above a level of a lower surface of the flat plate.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 11, 2019
    Assignee: Kyocera Corporation
    Inventors: Takuji Okamura, Akihiko Funahashi
  • Patent number: 10312383
    Abstract: The present invention applies to the technical field of photoelectric detectors and provides a high-frequency photoelectric detector encapsulation base can-packaged by using a multi-layer ceramic, comprising a laminated multi-layer ceramic substrate, wherein the multi-layer ceramic substrate is welded with pins at a bottom and provided with a metal ring at a top; an upper surface and a lower surface of each layer of the ceramic substrate are both plated with a conductive metal layer; circuit connection holes are distributed in each layer of the ceramic substrate; the upper surface of the multi-layer ceramic substrate is provided with two power contacts and two differential signal contacts; and the power contacts and the differential signal contacts penetrate through each layer of the ceramic substrate to be connected to the corresponding pins.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 4, 2019
    Assignee: WUHAN TELECOMMUNICATION DEVICES CO., LTD.
    Inventors: Zhicheng Su, Tuquan Chen, Xuyu Song
  • Patent number: 10304812
    Abstract: An optoelectronic device including a first integrated circuit that includes:—a substrate, having first and second opposite surfaces; and—groups of sets of light-emitting diodes resting on the first surface. The integrated circuit also includes:—in the substrate, first side elements for electrically insulating portions of the substrate around each set; and—for each group on the second surface, at least one first conductive contact, connected to the first terminal of the group, and one second conductive contact, connected to the second terminal of the group. The device includes a second integrated circuit containing:—third and fourth opposite surfaces; and—third conductive contacts, located on the third surface and electrically connected to the first and second conductive contacts. The first integrated circuit is attached onto the third surface of the second integrated circuit.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 28, 2019
    Assignee: Aledia
    Inventors: Frédéric Mercier, Philipe Gilet, Xavier Hugon
  • Patent number: 10269401
    Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Boyoung Seo, Seongui Seo, Gwanhyeob Koh, Yongkyu Lee
  • Patent number: 10249754
    Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Liying Jiang, Siyuranga O. Koswatta, Junli Wang
  • Patent number: 10224429
    Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Liying Jiang, Siyuranga O. Koswatta, Junli Wang
  • Patent number: 10211337
    Abstract: To provide a high-withstand-voltage lateral semiconductor device in which ON-resistance or drain current density is uniform at an end portion and a center portion of the device in a gate width direction. A lateral N-type MOS transistor 11 formed on an SOI substrate includes a trench isolation structure 10b filled with an insulating film at an end portion of the transistor. An anode region 6 of a diode 12 is provided adjacent to a P-type body region 1 of the transistor through the trench isolation structure 10b and a cathode region 15 of the diode 12 is also provided adjacent to an N-type drain-drift region 4 of the transistor through the trench isolation structure 10b so as to cause electric field to be applied to the trench isolation structure 10b to be zero when a voltage is applied across the transistor.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: February 19, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventor: Shinichirou Wada
  • Patent number: 10199549
    Abstract: A structure according to embodiments of the invention includes a semiconductor light emitting device and an optical element disposed over the semiconductor light emitting device. The semiconductor light emitting device is disposed in a recess in the optical element. A reflector is disposed on a bottom surface of the optical element. A method according to embodiments of the invention includes disposing a semiconductor light emitting device on a substrate and forming a reflector adjacent the semiconductor light emitting device. An optical element is formed over the semiconductor light emitting device. The semiconductor light emitting device is removed from the substrate.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: February 5, 2019
    Assignee: Lumileds LLC
    Inventors: Jerome Chandra Bhat, Grigoriy Basin, Kenneth Vampola
  • Patent number: 10163792
    Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: John Jianhong Zhu, Jeffrey Junhao Xu, Choh Fei Yeap, Stanley Seungchul Song, Kern Rim