Patents Examined by Syed Gheyas
  • Patent number: 10229964
    Abstract: A display device includes a substrate including a first pixel region, a second pixel region having an area smaller than that of the first pixel region, and a peripheral region surrounding the first pixel region and the second pixel region, a second pixel provided in the second pixel region, a second line connected to the second pixel, an extension line extended to the peripheral region, a dummy part located in the peripheral region to overlap with the extension line, a power line connected to the first and second pixel regions, and a connection line located in the peripheral region to be connected to the dummy part, the connection line being electrically connected to a portion of the second pixel region, wherein the second pixel region includes a first sub-pixel region connected to the connection line and a second sub-pixel region except the first sub-pixel region.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keon Woo Kim, Ji Hyun Ka, Tae Hoon Kwon, Ho Kyoon Kwon, Min Ku Lee, Zail Lhee, Jin Tae Jeong, Seung Ji Cha, Byung Du Ahn, Jeong Ho Lee
  • Patent number: 10217646
    Abstract: Transition metal dry etch by atomic layer removal of oxide layers for device fabrication, and the resulting devices, are described. In an example, a method of etching a film includes reacting a surface layer of a transition metal species of a transition metal-containing film with a molecular oxidant species. The method also includes removing volatile fragments of the reacted molecular oxidant species to provide an oxidized surface layer of the transition metal species. The method also includes reacting the oxidized surface layer of the transition metal species with a molecular etchant. The method also includes removing the reacted oxidized surface layer of the transition metal species and the reacted molecular etchant by volatlilization.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Patricio E. Romero, John J. Plombon
  • Patent number: 10211091
    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myeong-Dong Lee, Keunnam Kim, Dongryul Lee, Minseong Choi, Jimin Choi, Yong Kwan Kim, Changhyun Cho, Yoosang Hwang
  • Patent number: 10211278
    Abstract: A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong
  • Patent number: 10211097
    Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Shao-Kuan Lee, Hai-Ching Chen
  • Patent number: 10193058
    Abstract: According to one embodiment, a magnetoresistive memory device includes a first magnetic layer, a second magnetic layer on one major surface side of the first magnetic layer via a first nonmagnetic layer, a third magnetic layer on the second magnetic layer via a first Ru layer, a sidewall insulating film on sides of the layers, a fourth magnetic layer on an other major surface side of the first magnetic layer via a second nonmagnetic layer, and a fifth magnetic layer on the fourth magnetic layer via a second Ru layer. The reversed magnetic field of the second magnetic layer is smaller than that of the third and fourth magnetic layers, and the reversed magnetic field of the fifth magnetic layer is smaller than that of the third and fourth magnetic layers.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: January 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masayoshi Iwayama
  • Patent number: 10186618
    Abstract: An object is to achieve high electrical characteristics (a high on-state current value, an excellent S value, and the like) and a highly reliable semiconductor device. A high on-state current value is achieved, whereby a further reduction in channel width (W) is achieved. A second conductive layer functioning as a gate electrode has a function of electrically surrounding side surfaces of a semiconductor film in a cross section in a channel width direction. With this structure, on-state current of a transistor can be increased. To achieve a semiconductor device with less hot-carrier degradation, the gate electrode has a tapered portion.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10181447
    Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 15, 2019
    Assignee: Invensas Corporation
    Inventors: Chok J. Chia, Qwai H. Low, Patrick Variot
  • Patent number: 10177241
    Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Hoon Kim, Min Gyu Sung
  • Patent number: 10163643
    Abstract: A method of forming a semiconductor device includes etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Keng-Chuan Chang, Ting-Siang Su
  • Patent number: 10163939
    Abstract: The present disclosure provides a thin film transistor array substrate and a display device implementing the same. The thin film transistor array substrate includes a substrate; a first signal line formed on the substrate; and a thin film transistor formed on the substrate, and an active layer of the thin film transistor and the first signal line are located on different layers above the substrate and projections of them on a plane where the substrate is located overlap with each other at at least two positions. The present disclosure may improve wiring efficiency and reliability of the thin film transistor array substrate.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: December 25, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping Long, Yong Qiao
  • Patent number: 10163709
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 10163894
    Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
  • Patent number: 10164091
    Abstract: A circuit can include a field-effect transistor having a body, a drain, a gate, and a source. In an embodiment, the circuit can further include a bipolar transistor having a base and a collector, wherein the collector of the bipolar transistor is coupled to the body of the field-effect transistor; and the drain of the field-effect transistor is coupled to the base of the bipolar transistor. In another embodiment, the circuit can include a diode having an anode and a cathode, wherein the source of the field-effect transistor is coupled to the anode of the diode, and the gate of the field effect transistor is coupled to the cathode of the diode. In another aspect, an electronic device can include one or more physical structures that correspond to components within the circuits.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 25, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gary Horst Loechelt
  • Patent number: 10163946
    Abstract: An image sensor may include a lower device that includes logic transistors, an intermediate device that is formed over the lower device and includes a Correlated Double Sampling (CDS) circuit and a capacitor, and an upper device that is formed over the intermediate device and includes a photodiode, a floating diffusion region, and a transfer gate electrode.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventor: Young-Jun Kwon
  • Patent number: 10157851
    Abstract: The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Joon Kim, Jung Ho Shim, Dae Hyun Park, Han Kim
  • Patent number: 10153273
    Abstract: A semiconductor device is provided that comprises a base structure, a first channel layer overlying the base structure, a second channel layer overlying the first channel layer, and first, second, and third ohmic contacts overlying the second channel layer. The semiconductor device further comprises a metal-semiconductor heterodimension field effect transistor that is formed between the first and second ohmic contacts, the metal-semiconductor heterodimension field effect transistor including a first gate formed through the first and second channel layers. The semiconductor device yet further comprises a high electron mobility transistor formed between the second and third ohmic contacts, the high electron mobility transistor including a second gate formed through the second channel layer without extending through the first channel layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 11, 2018
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Roger S. Tsai, Weidong Liu, Yeong-Chang Chou
  • Patent number: 10147823
    Abstract: A transistor with stable electrical characteristics. A semiconductor device that includes an oxide semiconductor, a first conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The oxide semiconductor is positioned over the first insulator. The second insulator is positioned over the oxide semiconductor. The third insulator is positioned over the second insulator. The first conductor is positioned over the third insulator. The fourth insulator is positioned over the first conductor. The fourth insulator includes a region in contact with a top surface of the second insulator. The oxide semiconductor includes a region overlapping with the first conductor with the second insulator and the third insulator positioned therebetween. When seen from above, a periphery of the first insulator and a periphery of the second insulator are located outside a periphery of the oxide semiconductor.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10141283
    Abstract: An objective of the present invention is to provide a sinterable bonding material excellent in sinterability. The present invention relates to a sinterable bonding material comprising a silver filler and an organic base compound as a sintering promoter.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 27, 2018
    Assignees: Henkel AG & Co. KGaA, Henkel IP & Holding GmbH
    Inventors: Hajime Inoue, Tadashi Takano
  • Patent number: 10134907
    Abstract: Disclosed is a low temperature polysilicon array substrate and its manufacturing method. The method includes: forming a light-shielding layer, a buffer layer and U-type polysilicon patterns successively on a glass substrate; doping channels of the U-type polysilicon patterns in the active area and then heavily N+ doping these U-type polysilicon patterns; forming a gate insulation layer and etching first via holes; forming a gate line, a source and lightly-doped regions of the N-type double-gate transistor; and heavily P+ doping U-type polysilicon patterns in the non-active area.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 20, 2018
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuan Guo