Abstract: According to one embodiment, a magnetoresistive memory device includes a magnetoresistive element of a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first and second magnetic layers, and an insulating layer of a group III-V compound provided on a side of the first magnetic layer of the magnetoresistive element, the insulating layer including an chemical element of group II, group IV, or group VI.

Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. A gate overlies the body isolation well between the source and the drain, and an isolating structure is formed within the body isolation well. The isolating structure sections the source into a plurality of source sections with the plurality of source sections adjacent to one gate.

Abstract: A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

Abstract: A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

Abstract: Disclosed is an organic light emitting device. The organic light emitting device includes a first emission unit configured to include a common blue emission material layer which is included in common in a plurality of pixels emitting lights having different wavelength ranges, a second emission unit configured to include a red emission material layer, a green emission material layer, and a blue emission material layer which respectively emit lights having different wavelength ranges, a charge generation layer disposed between the first emission unit and the second emission unit, a first electrode formed as a reflective electrode, and configured to supply an electric charge having a first polarity to the first emission unit and the second emission unit, and a second electrode formed as a semi-transmissive electrode, and configured to supply an electric charge having a second polarity to the first emission unit and the second emission unit.

Abstract: A highly reliable semiconductor device which uses an oxide semiconductor film for a backplane is provided. A semiconductor device includes a first conductive film, a first insulating film over the first conductive film, an oxide semiconductor film which is over the first insulating film and overlaps with the first conductive film, a second insulating film over the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film through an opening portion included in the second insulating film. The second insulating film overlaps with a region of the oxide insulating film in which a carrier flows between the pair of second conductive films and overlaps with end portions of the oxide semiconductor film.

Abstract: To prevent cracks on a sealing glass or a substrate in a LED package in which a light-emitting device is sealed with a sealing glass. The LED package comprises a substrate, a LED mounted on the substrate, and a sealing glass for sealing a LED formed on the substrate. A wiring pattern being connected to an electrode of the LED is formed on the surface of the substrate. A back electrode pattern is formed on the rear surface of the substrate. A columnar via is formed in the substrate. Thus, the wiring pattern on the surface of the substrate and the back electrode pattern on the rear surface of the substrate are electrically connected. A softening point of the substrate is set higher than softening point of the sealing glass.

Abstract: In a semiconductor device using a nitride semiconductor, a MISFET is prevented from having deteriorated controllability which will otherwise occur when a tungsten film, which configures a gate electrode of the MISFET, has a tensile stress. A gate electrode of a MISFET having an AlGN/GaN heterojunction is formed from a tungsten film having grains with a relatively small grain size and having no tensile stress. The grain size of the grains of the tungsten film is smaller than that of the grains of a barrier metal film configuring the gate electrode and formed below the tungsten film.

Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.

Abstract: A magnetic domain wall (MDW) motion device. The MDW motion device may include a ferromagnetic layer with perpendicular magnetic anisotropy and non-magnetic metal layers extending parallel to and in contact with the ferromagnetic layer. The ferromagnetic layer may include first ferromagnetic regions, which are arranged in an extension direction of the ferromagnetic layer, and second ferromagnetic regions, which are provided between an adjacent pair of the first ferromagnetic regions. The first and second ferromagnetic regions may have spin torque coefficients of opposite signs, and an MDW positioned near an interface between the first and second ferromagnetic regions may be moved by an in-plane current flowing through the non-magnetic metal layer.

Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.

Abstract: The present disclosure provides an array substrate. The array substrate includes a substrate having a display region with a plurality of pixel regions, each pixel region having two or more first regions; a common electrode line between two adjacent pixel regions; a gate line; a data line intersecting with the gate line; at least one of the gate line and the data line being in a second region between two adjacent first regions; and a pixel electrode having a hollowed-out pattern within a corresponding first region, pixel electrodes corresponding to the two or more first regions being a pixel electrode unit.

Abstract: A display apparatus includes a light emitting diode part and a thin film (TFT) panel configured to drive the light emitting diode part. The light emitting diode part includes a transparent support substrate, a plurality of light emitting diodes, a plurality of phosphor layers disposed on the support substrate covering at a first portion of the plurality of light emitting diodes and configured to emit light through a conversion of introduced light. Another display apparatus includes a light emitting diode part including a plurality of light emitting diodes and a TFT panel configured to drive the light emitting diode part. The TFT panel includes a panel substrate including a TFT driving circuit and a plurality of grooves formed on the panel substrate. The TFT panel also includes a plurality of phosphor layers the plurality of grooves and configured to emit light through wavelength conversion of introduced light.

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.

Abstract: A quantum dot having core-shell structure, including a core formed of ZnOzS1-z of wurtzite crystal structure of hexagonal crystal system; a first shell covering the core, and formed of AlxGayIn1-x-yN of wurtzite crystal structure of hexagonal crystal system; and a second shell covering the first shell, and formed of ZnOvS1-v of wurtzite crystal structure of hexagonal crystal system. At least one of v, x, y, and z is not zero and is not one; differences between the lattice constants along a-axis of the core, the first shell and the second shell are not greater than 1%; and the core, the first shell and the second shell form band offset structure of type II.

Abstract: In described examples, a method of forming a microelectromechanical device comprises: forming a first metallic layer comprising a conducting layer on a substrate; forming a first dielectric layer on the first metallic layer, wherein the first dielectric layer comprises one or more individual dielectric layers; forming a sacrificial layer on the first dielectric layer; forming a second dielectric layer on the sacrificial layer; forming a second metallic layer on the second dielectric layer; and removing the sacrificial layer to form a spacing between the second dielectric layer and the first dielectric layer. Removing the sacrificial layer enables movement of the second dielectric layer relative to the first dielectric layer in at least one direction.

Abstract: Provided is a method for manufacturing a solar cell with improved output characteristics. A hydrogen radical treatment, in which ions are not used, is performed on at least one of the first and second semiconductor layers (11, 13).

Abstract: A layer material which is particularly suitable for the realization of self-supporting structural elements having an electrode in the layer structure of a MEMS component. The self-supporting structural element is at least partially made up of a silicon carbonitride (Si1-x-yCxNy)-based layer.