Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

Abstract: Die may be thinned using a thinning and/or a polishing process. Such thinned die may be flexible and may change operational characteristics when flexed. The flexible die may be applied to a mechanical carrier (e.g., a PCB) of a card or device. Detection circuitry may also be provided on the PCB and may be used to detect changed operational characteristics. Such detection circuitry may cause a reaction to the changed characteristics by controlling other components on the card or device based upon the flex-induced changed characteristics. The thinned die may be stacked, interconnected, and encapsulated between sheets of laminate material to form a flexible card or device.

Abstract: A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.

Abstract: Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.

Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.

Abstract: A semiconductor package and a method of fabricating the same are provided. The semiconductor package may include a first semiconductor chip with a first circuit pattern, a second semiconductor chip disposed on the first semiconductor chip and provided with a second circuit pattern, and first and second connection structures penetrating the first and second semiconductor chips. The first connection structure may be electrically connected to the first circuit pattern and may be electrically disconnected from the second circuit pattern. The second connection structure may be electrically disconnected from the first circuit pattern and may be electrically connected to the second circuit pattern.

Abstract: The present invention relates to the production of III-N templates and also the production of III-N single crystals, III signifying at least one element of the third main group of the periodic table, selected from the group of Al, Ga and In. By adjusting specific parameters during crystal growth, III-N templates can be obtained that bestow properties on the crystal layer that has grown on the foreign substrate which enable flawless III-N single crystals to be obtained in the form of templates or even with large III-N layer thickness.

Abstract: A method of manufacturing a semiconductor device, includes: forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a raw material gas to a substrate in a process chamber, exhausting the raw material gas remaining in the process chamber through an exhaust line, supplying an amine-based gas; and exhausting the amine-based gas through the exhaust line with the supply of the amine-based gas stopped. A degree of valve opening of an exhaust valve disposed in the exhaust line is changed in multiple steps in the process of exhausting the amine-based gas.

Abstract: A system for depositing one or more layers, particularly layers including organic materials therein, is described. The system includes a load lock chamber for loading a substrate to be processed, a transfer chamber for transporting the substrate, a vacuum swing module provided between the load lock chamber and the transfer chamber, at least one deposition apparatus for depositing material in a vacuum chamber of the at least one deposition chamber, wherein the at least one deposition apparatus is connected to the transfer chamber; a further load lock chamber for unloading the substrate that has been processed, a further transfer chamber for transporting the substrate, a further vacuum swing module provided between the further load lock chamber and the further transfer chamber, and a carrier return track from the further vacuum swing module to the vacuum swing module, wherein the carrier return track is configured to transport the carrier under vacuum conditions and/or under a controlled inert atmosphere.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with respect to the fan-out substrate, and forming interconnection lines. At least one of the interconnection lines includes a first portion extending from the fan-out substrate to a target position on the cavity disposed between the fan-out substrate and one of the dies the one of the dies disposed at a detected position different from the target position, and a second portion extending from the one die to the fan-out substrate.

Abstract: A wafer processing laminate including a support, a temporary adhesive material layer formed on the support, and a wafer laminated on the temporary adhesive material layer, the wafer having a circuit-forming front surface and back surface to be processed, wherein the temporary adhesive material layer includes a complex temporary adhesive material layer having two-layered structure including a first temporary adhesive layer composed of a thermoplastic organopolysiloxane polymer layer (A) having a film thickness of less than 100 nm and a second temporary adhesive layer composed of a thermosetting siloxane-modified polymer layer (B), the first temporary adhesive layer being releasably laminated to the front surface of the wafer, the second temporary adhesive layer being releasably laminated to the first temporary adhesive layer and the support. A temporary adhesive material for a wafer processing which withstand a thermal process at high temperature exceeding 300° C.

Abstract: The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.

Abstract: An array substrate is disclosed. The array substrate comprises a base substrate (4) and signal lines on the base substrate (4). The signal lines comprises a plurality of conductive layers (11, 12) in different layers, and the plurality of conductive layers (11, 12) are provided with insulation layers (21) therebetween, and are connected in parallel through one or more vias (3). Embodiments of the present disclosure further disclose a method for manufacturing the array substrate.

Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

Abstract: Quantum dot semiconductor nanoparticle compositions that incorporate ions such as zinc, aluminum, calcium, or magnesium into the quantum dot core have been found to be more stable to Ostwald ripening. A core-shell quantum dot may have a core of a semiconductor material that includes indium, magnesium, and phosphorus ions. Ions such as zinc, calcium, and/or aluminum may be included in addition to, or in place of, magnesium. The core may further include other ions, such as selenium, and/or sulfur. The core may be coated with one (or more) shells of semiconductor material. Example shell semiconductor materials include semiconductors containing zinc, sulfur, selenium, iron and/or oxygen ions.

Abstract: A substrate processing system for depositing film on a substrate includes a processing chamber defining a reaction volume and including a substrate support for supporting the substrate. A gas delivery system is configured to introduce process gas into the reaction volume of the processing chamber. A plasma generator is configured to selectively generate RF plasma in the reaction volume. A clamping system is configured to clamp the substrate to the substrate support during deposition of the film. A backside purging system is configured to supply a reactant gas to a backside edge of the substrate to purge the backside edge during the deposition of the film.

Abstract: An OLED display device and fabrication method thereof, a display panel and a display device are provided, and the method includes: providing a substrate having an anode layer and a hole injection layer; providing a first molding substrate and a second molding substrate, with a first cavity block being formed on the first molding substrate and a second cavity block being formed on the second molding substrate by a micro mechanical electro system technology, wherein the first cavity block is configured for preparing a hole transport layer corresponding to a sub-pixel of the pixel unit, and the second cavity block is configured for preparing an organic light emitting layer corresponding to a sub-pixel of the pixel unit; filling the first cavity block with a solution of a hole transport material by soaking technology, solidifying to obtain a hole transport layer, and filling the second cavity block with a solution of an organic light emitting material by soaking technology, solidifying to obtain an organic light

Abstract: There is provided a laser processing method of laser-processing a wafer along a plurality of streets formed in a lattice manner on a top surface of the wafer, the wafer having devices formed in a plurality of regions partitioned by the streets, the laser processing method including: a wafer holding step of holding an undersurface of the wafer by a chuck table; a resin supplying step of supplying a water-soluble liquid resin to the top surface of the wafer; a protective film forming step of forming a protective film P on the wafer as a result of drying the water-soluble liquid resin by irradiating the water-soluble liquid resin with light from a xenon flash lamp; a laser irradiating step of irradiating the wafer with a laser beam through the protective film along the streets; and a cleaning step of cleaning the wafer after the laser irradiating step.