Patents Examined by Syed I Gheyas
  • Patent number: 10804221
    Abstract: In one embodiment, a substrate treatment apparatus includes a substrate holder configured to hold a substrate provided with a film. The apparatus further includes a film treatment module configured to treat the film in accordance with warpage of the substrate such that the film includes a first region having a first film quality or a first film thickness and a second region having a second film quality or a second film thickness different from the first film quality or the first film thickness.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fuyuma Ito, Yasuhito Yoshimizu, Hakuba Kitagawa
  • Patent number: 10790228
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Patent number: 10790379
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming one or more vertical fins on a semiconductor substrate with a hardmask on a top surface of the one or more vertical fins. The method includes forming an opening in the hardmask and the one or more vertical fins and in a portion of the semiconductor substrate to form a plurality of vertical fins. The method includes depositing an anchor layer in the opening. The method includes depositing a liner layer on sidewalls of each of the vertical fins and above a top surface of the semiconductor substrate. The method includes forming an angled recessed region in the exposed portion of each of the vertical fins below the liner layer and in the semiconductor substrate. The method includes forming a bottom source/drain region in the angled recessed region.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Ruilong Xie, Kangguo Cheng
  • Patent number: 10770357
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 8, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoit Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
  • Patent number: 10763391
    Abstract: The present disclosure provides a display panel, a display device comprising such a display panel, and a method for processing defective pixels of such a display panel. The display panel comprises: a substrate; a plurality of pixel units on the substrate and arranged in an array. Each of the pixel units includes a light emitting region and a driving circuit region. In each of the pixel units, the driving circuit region includes a transistor, the light emitting region includes a first electrode, and the first electrode is electrically coupled to a first terminal of the transistor. In a row direction or a column direction of the plurality of pixel units arranged in an array, light emitting regions of two adjacent pixel units are adjacent to each other.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: September 1, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yicheng Lin, Cuili Gai, Baoxia Zhang, Ling Wang, Quanhu Li, Pan Xu
  • Patent number: 10756257
    Abstract: Provided is a magnetoresistance effect device comprising a magnetoresistance effect element including a first ferromagnetic layer, a second ferromagnetic layer and a spacer layer and a high-frequency signal line. The high-frequency signal line includes an overlapping part disposed at a position overlapping the magnetoresistance effect element and a non-overlapping part disposed at a position not overlapping the magnetoresistance effect element in a plan view from a stacking direction. At least a part of the non-overlapping part is formed to be thicker than at least a part of the overlapping part. A distance in the stacking direction between a virtual plane including a surface on the side of the overlapping part of the first ferromagnetic layer and a center line in the high-frequency signal line in the stacking direction is shorter in at least a part of the overlapping part than in at least a part of the non-overlapping part.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 25, 2020
    Assignee: TDK CORPORATION
    Inventor: Naomichi Degawa
  • Patent number: 10756172
    Abstract: A semiconductor device having a silicon-on-insulator (SOI) structure in which a source region and a drain region extend along a longitudinal direction that is a direction along a longer side of sides facing each other, and are disposed side-by-side in a lateral direction that is a direction perpendicular to the longitudinal direction. In a plan view, a body region extends along the longitudinal direction and is surrounded by a drift region and an insulating region. A space between the insulating region and the body region in the lateral direction becomes narrower from the center to the end of the body region in the longitudinal direction. This achieves high breakdown voltage in the semiconductor device.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 25, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Teruhisa Ikuta, Hiroshi Sakurai, Satoru Kanai
  • Patent number: 10749025
    Abstract: A semiconductor device having a contact trench is provided. The semiconductor device including: a semiconductor substrate; a drift region of the first conductivity type provided on an upper surface side of the semiconductor substrate; a base region of the second conductivity type provided above the drift region; a source region of the first conductivity type provided above the base region; two or more trench portions provided penetrating through the source region and the base region from an upper end side of the source region; a contact trench provided in direct contact with the source region between adjacent trench portions; and a contact layer of the second conductivity type provided below the contact trench, is provided. A peak of a doping concentration of the contact layer is positioned shallower than a position of a lower end of the source region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10734218
    Abstract: There is provided a process of forming a film containing a metal element, an additional element different from the metal element and at least one of nitrogen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a first precursor gas containing the metal element and a second precursor gas containing the additional element to the substrate so that supply periods of the first precursor gas and the second precursor gas at least partially overlap with each other; and (b) supplying a reaction gas containing the at least one of nitrogen and carbon to the substrate.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 4, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Arito Ogawa, Atsuro Seino
  • Patent number: 10734224
    Abstract: A method of forming a semiconductor device includes providing a starting structure including a substrate having thereon a plurality of gate regions alternately arranged with a plurality of source/drain (S/D) regions, wherein each of the gate regions includes a nanochannel structure having an intermediate portion surrounded by a replacement gate, and opposing end portions surrounded by respective gate spacers such that the nanochannel structure extends through the replacement gate and the gate spacers of the gate region. Each of the S/D regions includes an S/D structure extending through the S/D region to connect nanochannel structures of first and second adjacent gate regions provided on opposing sides of the S/D region respectively.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton Devilliers
  • Patent number: 10734419
    Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor including a first and second pair of photodetectors. The pixel sensor includes the first and second pair of photodetectors in a semiconductor substrate. The first pair of photodetectors are reflection symmetric with respect to a first line positioned at a midpoint between the first pair of photodetectors. The second pair of photodetectors are reflection symmetric with respect to a second line that intersects the first line at a center point. A first plurality of transistors overlying the semiconductor substrate laterally offset the first pair of photodetectors. A second plurality of transistors overlying the semiconductor substrate laterally offset the first plurality of transistors. The first and second pair of photodetectors are laterally between the first and second plurality of transistors. The first and second plurality of transistors are point symmetric with respect to the center point.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Seiji Takahashi
  • Patent number: 10734397
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 4, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Cheng Zhou, Bin Yuan, QingBo Liu, Song Man Xu, Siying Liu, Rui Gong, Zhiguo Zhao, Zhaoyun Tang, Zhiliang Xia, Zongliang Huo
  • Patent number: 10727111
    Abstract: A method includes: forming a first conductive structure in a first dielectric layer; forming a conductive protection structure that is coupled to at least part of the first conductive structure; forming a second dielectric layer over the first dielectric layer; forming a via hole extending through at least part of the second dielectric layer to expose a portion of the conductive protection structure; cleaning the via hole; and refilling the via hole with a conductive material to form a via structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufaturing Co., Ltd.
    Inventors: Hung-Chih Yu, Chien-Mao Chen
  • Patent number: 10714347
    Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Uei Jang, Ya-Yi Tsai, Ryan Chia-Jen Chen, An Chyi Wei, Shu-Yuan Ku
  • Patent number: 10714405
    Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip, and a thermal redistribution pattern which are disposed on a package substrate. The thermal redistribution pattern may include a first end portion disposed in a high temperature region adjacent to the first semiconductor chip, a second end portion disposed in a low temperature region adjacent to the second semiconductor chip, and an extension portion connecting the first end portion to the second end portion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae Woong Lee
  • Patent number: 10707293
    Abstract: Each of pixels includes: a transparent upper electrode covering at least a part of the first region and at least a part of the second region; a reflective lower electrode disposed in the second region; a light-emitting film disposed between the transparent upper electrode and the reflective lower electrode, the light-emitting film being configured to emit light in response to supplied electric current; a thin film transistor disposed lower than the reflective lower electrode in the second region, the thin film transistor having a channel made of a transparent oxide; and a transparent low-resistive film that is made of the transparent oxide and interconnects the power-source potential supply line and the transparent upper electrode, the transparent low-resistive film being separate from an oxide film that is made of the transparent oxide and includes the channel and having a resistance lower than a resistance of the channel.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 7, 2020
    Assignee: TIANMAN JAPAN, LTD.
    Inventor: Kazushige Takechi
  • Patent number: 10692811
    Abstract: A semiconductor structure includes a first anti-fuse structure, a second anti-fuse structure and a first metal layer. The second anti-fuse structure is disposed over the first anti-fuse structure. The first metal layer is between the first anti-fuse structure and the second anti-fuse structure. A first contact is disposed between the first anti-fuse structure and the first metal layer to connect thereof. A second contact is disposed between the second anti-fuse structure and the first metal layer to connect thereof.
    Type: Grant
    Filed: December 2, 2018
    Date of Patent: June 23, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tsang-Po Yang, Shian-Jyh Lin, Jui-Hsiu Jao
  • Patent number: 10679905
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of first gate structures on a first region of a substrate, a plurality of second gate structures on a second region of the substrate, and a first stress layer on both sides of each first gate structure; forming a first-region mask layer on the first stress layer; forming a second stress layer on both sides of each second gate structure; forming a contact-hole etch stop layer on the second stress layer; forming a plurality of first contact holes on the first stress layer and a plurality of second contact holes on the second stress layer to expose the contact-hole etch stop layer; at least partially removing the contact-hole etch stop layer in each first contact hole; and removing the first-region mask layer in each first contact hole and the contact-hole etch stop layer in each second contact hole.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10672631
    Abstract: A method and a system for thinning a substrate are provided. The method includes at least the following steps. A liquid seal is provided at an interface between a chuck and a substrate disposed on the chuck. The substrate is thinned during the liquid seal is provided.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • Patent number: 10673425
    Abstract: A current limiting resistor opposes a p-type anode region of a bootstrap diode in a depth direction, across an insulating film. The current limiting resistor is configured by poly-silicon layers constituting poly-silicon resistors, and a poly-silicon connector that is a connector connected to a limiting resistor electrode. The poly-silicon layers are disposed further outside than is the poly-silicon connector and each has a first end connected to the poly-silicon connector. The poly-silicon layers each have a second end and a part that is toward the second end and that is in contact with an anode electrode via a contact hole. Further, the poly-silicon layers are disposed evenly between a part thereof connected to the poly-silicon connector and the contact hole.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 2, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura