Patents Examined by Syed I Gheyas
  • Patent number: 11322595
    Abstract: The disclosure provides a heterojunction bipolar transistor and a preparation method thereof. Since an emitter region has the same physical structure as a base region, and improves frequency characteristics of the device; Simultaneously with biaxial strain, uniaxial strain is introduced. Carrier transmission time in the collector region will be effectively reduced. By this structure, the width of the effective collector region is reduced, the collector junction capacitance is reduced, and the frequency characteristics of the device are further improved; an appropriate choice of the thickness of the Si cap layer can effectively reduce the accumulation of carriers at an interface and increase the gain of the device; at the same time, the preparation method of the bipolar transistor is completely compatible with a 90-nanometer CMOS process, which effectively reduces the development and manufacturing cost of the device.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 3, 2022
    Assignee: Yanshan University
    Inventors: Chunyu Zhou, Zuowei Li, Guanyu Wang, Xin Geng
  • Patent number: 11322626
    Abstract: Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a first layer having a first type of dopant, a second layer forming a region with at least ten times lower concentration of dopants compared to the adjacent layers, and a third layer having a second type of dopant that is opposite to the first type of dopant. The first layer of a second DSRD is positioned on top of the third layer of first DSRD. The first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 3, 2022
    Assignees: Lawrence Livermore National Security, LLC, BAE Systems Land & Armaments L.P., The Government of the United States, as represented by the Secretary of the Army
    Inventors: Lars F. Voss, Adam M. Conway, Luis M. Hernandez, Mark S. Rader
  • Patent number: 11309402
    Abstract: A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Yosuke Kita
  • Patent number: 11309409
    Abstract: This disclosure relates to a semiconductor device and corresponding method of manufacturing the semiconductor device. The semiconductor device includes a MOS transistor device die and a SiGe diode. The SiGe diode is integrally arranged on the MOS transistor device die, so that the SiGe diode is electrically connected between a source connection and drain connection of the MOS transistor device die.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 19, 2022
    Assignee: Nexperia B.V.
    Inventor: Tim Böttcher
  • Patent number: 11309401
    Abstract: The present disclosure provides a method for manufacturing a thin film transistor and a thin film transistor, which includes providing a substrate; forming an active layer on the substrate and patterning the active layer, the active layer is made of cubic boron nitride; and forming a first insulating layer, a gate electrode metal layer, a second insulating layer, a source and drain metal layer and a flat layer on the active layer successively. the method for manufacturing a thin film transistor and the thin film transistor of the present disclosure employ cubic boron nitride instead of polysilicon as active layer materials, CVD process is directly applied to form the active layer with cubic boron nitride.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: April 19, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Tianyu Huang
  • Patent number: 11296237
    Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 5, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Luigi Colombo, Arup Polley
  • Patent number: 11296200
    Abstract: A semiconductor device including one or more transistors is disclosed. The semiconductor device includes a first active region disposed over a well region of a substrate, a plurality of dummy active regions disposed around the first active region, and a gate disposed to traverse the first active region, wherein a portion of the gate is disposed to overlap with at least one of the plurality of dummy active regions and is electrically coupled to the at least one of the plurality of dummy active regions.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Kil Seo
  • Patent number: 11289591
    Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
  • Patent number: 11289508
    Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. For example, a method for forming a 3D memory device is provided. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a substrate. A staircase structure is formed on at least one side of the dielectric stack. Dummy channel holes and dummy source holes extending vertically through the staircase structure are formed. A subset of the dummy channel holes is surrounded by the dummy source holes. A dummy channel structure is formed in each dummy channel hole, and interleaved conductive layers and dielectric layers are formed in the staircase structure by replacing, through the dummy source holes, the sacrificial layers in the staircase structure with the conductive layers. A spacer is formed along a sidewall of each dummy source hole to cover the conductive layers in the staircase structure, and a contact is formed within the spacer in each dummy source hole.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 29, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenyu Hua, Fandong Liu, Zhiliang Xia
  • Patent number: 11282947
    Abstract: A heterojunction bipolar transistor may include a base epitaxially grown on a collector, an emitter epitaxially grown on the base, the emitter and the base being patterned into a fin, and a silicon oxide layer formed on sidewalls of the fin, the silicon oxide layer separating the base from a spacer. The heterojunction bipolar transistor may include the spacer formed on top of the silicon oxide layer and an interlayer dielectric formed on top of the spacer. The heterojunction bipolar transistor may also include a silicon germanium oxide layer formed on sidewalls of the base. The base may be made of silicon germanium. The emitter and the collector may be made of silicon. The base may be doped with a p-type dopant. The emitter and the collector may be doped with a n-type dopant.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Alexander Reznicek, Choonghyun Lee, Soon-Cheon Seo
  • Patent number: 11283021
    Abstract: A semiconductor layer (2,3) is provided on a substrate (1). A gate electrode (4), a source electrode (5) and a drain electrode (6) are provided on the semiconductor layer (3). A strongly correlated electron system material (12) is connected between the gate electrode (4) and the source electrode (5).
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hajime Sasaki
  • Patent number: 11276773
    Abstract: A semiconductor device includes: first diode trench gates extending along a first main surface from a first end side of a cell region toward a second end side thereof opposite to the first end side, the first diode trench gates being disposed adjacent to each other at a first spacing; a boundary trench gate connected to end portions of the first diode trench gates and extending in a direction intersecting a direction of extension of the first diode trench gates; and second diode trench gates having end portions connected to the boundary trench gate and extending toward the second end side of the cell region.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Soneda, Kenji Harada, Kakeru Otsuka
  • Patent number: 11271097
    Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes Swenberg
  • Patent number: 11270888
    Abstract: A device includes a source/drain (S/D) in a substrate and adjacent to a gate structure, wherein the S/D comprises a protrusion extending from a top surface of the S/D, and the protrusion has a tapered profile. The device further includes a contact plug electrically connected to the protrusion.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Keng-Chuan Chang, Ting-Siang Su
  • Patent number: 11257940
    Abstract: A High Mobility Electron Transistor (HEMT) and a capacitor co-formed on an integrated circuit (IC) share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT, which also functions in lieu of a base metal layer of a conventional capacitor. In another embodiment, a dialectic layer of the capacitor may be formed in a passivation step of forming the HEMT. In another embodiment, a metal contact of the HEMT (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor. In these embodiments, one or more processing steps required to form a conventional capacitor are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 22, 2022
    Assignee: Cree, Inc.
    Inventors: Evan Jones, Jeremy Fisher
  • Patent number: 11257936
    Abstract: According to some embodiments in this application, a method for making a JFET device is disclosed in the following steps: forming a substrate; performing ion implantation on the first region and the second region of the substrate to form a deep N-type well, wherein the deep N-type well is formed with at least two sub-wells region; forming a field oxide in the second region; forming a P-type well in one side of the sub-well in the deep N-type well; performing P-type ion implantation on the third region and the fourth region to respectively form a first P-type heavily doped region and a second P-type heavily doped region; and performing N-type ion implantation on the fifth region, the sixth region, and the seventh region to respectively form a first N-type heavily doped region, a second N-type heavily doped region, and a third N-type heavily doped region.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: February 22, 2022
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Ying Cai, Feng Jin
  • Patent number: 11251290
    Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: February 15, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Patent number: 11251342
    Abstract: A stabilized fluoride phosphor for light emitting diode (LED) applications includes a particle comprising manganese-activated potassium fluorosilicate and an inorganic coating on each of the particles. The inorganic coating comprises a silicate. A method of making a stabilized fluoride phosphor comprises forming a reaction mixture that includes particles comprising a manganese-activated potassium fluorosilicate; a reactive silicate precursor; a catalyst; a solvent; and water in an amount no greater than about 10 vol. %. The reaction mixture is agitated to suspend the particles therein. As the reactive silicate precursor undergoes hydrolysis and condensation in the reaction mixture, an inorganic coating comprising a silicate is formed on the particles. Thus, a stabilized fluoride phosphor is formed.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 15, 2022
    Assignee: CREELED, INC.
    Inventors: Ryan Gresback, Kenneth Lotito, Linjia Mu
  • Patent number: 11251084
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Alexis Gauthier, Gregory Avenier
  • Patent number: 11244919
    Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Kuo-Ching Hsu, Mirng-Ji Lii