Patents Examined by Syed I Gheyas
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Patent number: 11855195Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.Type: GrantFiled: October 25, 2021Date of Patent: December 26, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Patent number: 11854870Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: GrantFiled: August 30, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11855197Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.Type: GrantFiled: January 20, 2022Date of Patent: December 26, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Shesh Mani Pandey, Alexander M. Derrickson, Judson R. Holt, Vibhor Jain
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Patent number: 11855196Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.Type: GrantFiled: October 25, 2021Date of Patent: December 26, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Patent number: 11855150Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.Type: GrantFiled: May 27, 2022Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Yun-Yuan Wang, Chih-Hsiang Hsiao, I-Chih Ni, Chih-I Wu
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Patent number: 11837653Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.Type: GrantFiled: December 20, 2021Date of Patent: December 5, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Jagar Singh, Alexander M. Derrickson, Alvin J. Joseph, Andreas Knorr, Judson R. Holt
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Patent number: 11830938Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.Type: GrantFiled: March 6, 2023Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zi-Ang Su, Chih Chieh Yeh, Ming-Shuan Li
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Patent number: 11823984Abstract: A method for fabricating a semiconductor device includes providing a substrate; sequentially forming a layer of first conductive material, a layer of second conductive material, a layer of third conductive material, and an anti-reflective coating layer over the substrate; performing a plug etch process to turn the layer of first conductive material into a bottom conductive layer on the substrate, turn the layer of second conductive material into a middle conductive layer on the bottom conductive layer, and turn the layer of third conductive material into a top conductive layer on the middle conductive layer; selectively forming an insulating covering layer on a sidewall of the middle conductive layer, wherein the bottom conductive layer, the middle conductive layer, the top conductive layer, and the insulating covering layer together configure a plug structure; and forming a first dielectric layer on the substrate and surrounding the plug structure.Type: GrantFiled: October 8, 2021Date of Patent: November 21, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11817353Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: GrantFiled: January 4, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Alexis Gauthier, Gregory Avenier
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Patent number: 11817493Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.Type: GrantFiled: December 8, 2021Date of Patent: November 14, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Mari Saji, Atsushi Kurokawa, Koshi Himeda
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Patent number: 11817486Abstract: A semiconductor device and a method of making a semiconductor device are described. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.Type: GrantFiled: December 26, 2022Date of Patent: November 14, 2023Assignee: NXP USA, Inc.Inventors: James Albert Kirchgessner, Jay Paul John, Steven Kwan
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Patent number: 11817484Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.Type: GrantFiled: September 27, 2022Date of Patent: November 14, 2023Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Franck Julien, Stephan Niel, Leo Gave
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Patent number: 11817477Abstract: A power semiconductor device includes a first electrode, a substrate, a first epitaxy layer, a second epitaxy layer, a gate electrode, and a second electrode. The substrate is located on the first electrode, and the substrate includes an active region and a termination region surrounding the active region. The first epitaxy layer is located on the substrate, and the first epitaxy layer has a first conductive type. The first epitaxy layer includes a first doped area and a second doped area. The first doped area has the first conductive type and is located in the termination region and the active region. The second doped area has a second conductive type and is located in the termination region. The second epitaxy layer is located on the first epitaxy layer. The gate electrode and the second electrode are located on the second epitaxy layer and are in the active region.Type: GrantFiled: April 15, 2022Date of Patent: November 14, 2023Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: Chung-Yi Chen
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Patent number: 11810969Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.Type: GrantFiled: October 25, 2021Date of Patent: November 7, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Haiting Wang, Alexander Derrickson, Jagar Singh, Vibhor Jain, Andreas Knorr, Alexander Martin, Judson R. Holt, Zhenyu Hu
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Patent number: 11810952Abstract: A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction.Type: GrantFiled: May 15, 2022Date of Patent: November 7, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
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Patent number: 11804542Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region.Type: GrantFiled: December 21, 2021Date of Patent: October 31, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Alexander M. Derrickson, Arkadiusz Malinowski, Jagar Singh, Mankyu Yang, Judson R. Holt
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Patent number: 11798953Abstract: The present application provides an array substrate and a display panel. The array substrate includes fan-out regions and an inverted region formed between two adjacent fan-out regions. The array substrate includes metal lines and floating metal lines. The metal lines include first metal lines in the fan-out region and second metal lines in the inverted triangle region. The floating metal lines include a first floating metal line arranged between the first metal lines and the second metal lines. The array substrate includes an alignment film arranged on the metal lines and the floating metal lines.Type: GrantFiled: November 24, 2020Date of Patent: October 24, 2023Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Zhida Xu
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Patent number: 11799011Abstract: Provided is a semiconductor epitaxial wafer, including a substrate, a first epitaxial structure, a first ohmic contact layer and a second epitaxial stack structure. It is characterized in that the ohmic contact layer includes a compound with low nitrogen content, and the ohmic contact layer does not induce significant stress during the crystal growth process. Accordingly, the second epitaxial stack structure formed on the ohmic contact layer can have good epitaxial quality, thereby providing a high-quality semiconductor epitaxial wafer for fabricating a GaAs integrated circuit or a InP integrated circuit. At the same time, the ohmic contact properties of ohmic contact layers are not affected, and the reactants generated during each dry etching process are reduced.Type: GrantFiled: April 7, 2022Date of Patent: October 24, 2023Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.Inventors: Chao-Hsing Huang, Yu-Chung Chin, Van-Truong Dai
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Patent number: 11798995Abstract: A first collector layer is composed of n-type InP (n-InP) doped with Si at a low concentration. A second collector layer is composed of non-doped InGaAs. A base layer is composed of p-type GaAsSb (p+-GaAsSb) doped with C at a high concentration. An emitter layer is composed of a compound semiconductor different from that of the base layer, and has an area smaller than the base layer in a plan view. An emitter layer can be composed of, for example, n-type InP (n-InP) doped with Si at a low concentration.Type: GrantFiled: June 4, 2019Date of Patent: October 24, 2023Assignee: Nippon Telegraph and Telephone CorporationInventors: Yuta Shiratori, Takuya Hoshi, Minoru Ida
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Patent number: 11791423Abstract: A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8·1015 cm?3. The drift region has a lightly n-doped drift layer and a lightly p-doped drift layer, arranged between the n-doped drift layer and the anode layer, both drift layers each have a layer thickness of at least 5 ?m. The cathode layer has a first section with a dopant concentration of at least 1·1017 cm?3 and a second section, arranged between the first section and the drift region, the second section has a layer thickness of at least 1 ?m and a dopant concentration gradient that increases in the direction of the first section up to a dopant concentration maximum. The dopant concentration maximum is smaller or equal to the dopant concentration of the first section.Type: GrantFiled: February 8, 2022Date of Patent: October 17, 2023Assignee: 3-5 Power Electronics GmbHInventors: Jens Kowalsky, Riteshkumar Bhojani, Volker Dudek