Abstract: Synchronization is maintained between a regional radio transmitter/receiver and a remote transmitter/receiver communicating across a TDMA channel by detecting time misalignment of communications from the remote transmitter/receiver to the regional transmitter/receiver, commanding the remote transmitter/receiver to adjust its transmission timing, and, until the remote transmitter/receiver has adjusted its transmission timing, looking for a synchronization pattern accompanying transmissions by the remoter transmitter/receiver during two discontinuous time intervals, one centered about a time of occurrence of the synchronization pattern before the command and another centered about an expected time of occurrence of the synchronization pattern in response to the command. Effectively, what would otherwise be a disadvantageously wide time window is split into two advantageously narrow time windows to avoid detection of false syncs. Fewer false syncs are detected, and speech quality is increased.

Abstract: A synchronizing pulse is produced upon detection of a frame codeword or frame-structured binary signal consisting of a first word repeated a plurality of times and at least one second word. A demultiplexer divides the incoming signal into n words which are advanced in parallel through n shift registers of a first memory matrix, followed by the next n words, and so on. A decoder determines whether the first word is stored in each register, and increments a respective one of n counters when the word is found. An addressing logic transforms the output into a binary number which controls a multiplexer which, in turn controls arrangement of bits in a second memory matrix. A synchronizing pulse is produced when the second memory matrix contains predetermined bits of the first and second word.

Abstract: A digital signal data retiming and clock extraction apparatus including a series of three data latches (111, 121, 131), connected in cascade, means for applying digital data signals to the first latch, means for clocking (701) the first and third latches in phase with the data signals input to the first latch, means for clocking the second latch in antiphase with the data signals input to the first latch, coincidence detection means (210) to which are applied the digital data signals (A) input to the first latch, the data signals output (B) of the second latch and the data signals output (C) of the third latch, the coincidence detection means being arranged to derive output data signals (X) in accordance with the algorithm X=B. (A-C), and a first phase lock loop feedback means (Q1, Q2, 301) whereby the output data signals (X) of the coincidence detection circuit control the timing of the clocking means to maintain the phase relationship with the digital data signals input to the first latch.

Abstract: Frontend LANs connecting plural stations are connected to plural nodes of a backbone LAN respectively. The backbone LAN is constituted by plural physical or logical links, and each node corresponds to each frontend LAN. A first data block is segmented into one or plural second data block units of fixed length and transferred to destination nodes, a bridge is provided in order to assemble the second data blocks into the first data block. The bridge can transmit the second data blocks to arbitrary links, and the receiving is performed through one link. The bridge a decoder also has a decoder for decoding whether the learning should be performed or not, based on the learning indication information existing in the second data block including the routing information.

Abstract: In a local area network station (12) for a wireless LAN, a threshold level circuit (62) includes a register (134) which stores a threshold value. The station receiver (42) monitors the transmission channel and provides a receive level signal indicative of the signal level received. Transmission of a data frame by the station transmitter (46) is permitted or deferred according as the receive level signal value is below or above the threshold level, regardless of whether or not the received signal derives from a transmission by a station in the receiving station's own LAN. The threshold is dynamically updated whenever the station (12) receives a data frame from its own LAN. An improved utilization of the wireless transmission channel is achieved.

Abstract: A system and method for correcting for Rayleigh interference of a signal transmitted upon a multi-path channel. The system adaptively calculates values of channel gain and noise variance of the channel upon which the signal is transmitted, and generates signals indicative of such calculations which are supplied to a decoder. The system may be utilized to form a portion of a coherent, or noncoherent receiver which receives encoded and differentially-encoded signals.

Abstract: A fault location arrangement for either electrical or optical digital transmission systems is provided by a distinct diagnostic signal at each of a series of regenerators which is used to modulate data signals. The modulated data signals are then recovered by demodulation and analyzed to determine the status of each regenerator. Diversion of signals by "loop-back" at each regenerator is also provided for.

Abstract: In a network system in which an interconnection is achieved between an LAN terminal connected to an LAN and an ISDN terminal linked with an ISDN via at least an LAN/ISDN inter-working unit coupling the LAN with the ISDN, the ISDN terminal develops a function to multiplex data link connections (communication paths) identified with respective data link connection identifiers (DLCIs) on ISDN channels. After conducting a call establishment to the ISDN terminal, the inter-working unit supplies the LAN terminal with an ISDN channel number and a DLCI designating an ISDN communication path. Thereafter, the LAN terminal sends an LAN frame having an OSI layer 2 header loaded with the communication path information to the inter-working unit. On receiving the LAN frame, the inter-working unit executes a format conversion to convert the LAN frame into an ISDN frame based on the ISDN communication path information.

Abstract: A unique word detection apparatus for detecting a unique word out of a demodulated signal resulting from the demodulation of a burst signal consisting of a carrier recovery section, a bit timing recovery section, a unique word section and a data section. The magnitude of the D.C. component of the demodulated signal is extracted, and the timing of the transition of this D.C. component from large to small is detected. An aperture signal designating the period in which to detect the unique word on the basis of the transition timing of the D.C. component generated, and the unique word out of the demodulated signal entered during the period designated by the aperture signal is accurately detected.

Abstract: A repeater for enhancing performance of a TDMA mobile radio system in poor signal areas has a bank of frequency agile, single channel amplifiers (13), and controller (14). The controller (14) scans the channel of the band and, upon identifying a channel carrying traffic, enables one of the amplifier units (13) to operate on that channel. Each of the amplifier units (13) includes a time slot activity detector (35) for detecting which time slot of a channel is active. The output of the activity detector (35) is passed to a logic control module (36), which controls the amplification of an active time slot via a time slot gate and power unit (38).

Abstract: A communication system such as a digital cordless telephone system comprises primary (or base) stations (PS) and secondary stations (SS). The primary stations over a local area are coupled to a system controller (14 or 15) which interfaces with the PSTN. A TDMA method is used for forward and reverse transmissions between a primary and a secondary station. For digitized speech transmission normally one duplex voice channel formed by one forward time slot (or physical channel) and one reverse time slot (or physical channel) in each frame is allocated for the transaction. For fast data rates it is desirable that additional duplex voice channels be made available quickly for the transmission of a fast data message, after which the additional duplex voice channels can be relinquished. In order to facilitate the rapid set-up of a data transaction, a map store in each data secondary station lists the usage and quality of all the duplex voice channels.

Abstract: A device for the transmission of digital data with at least two levels of protection, of the type providing for the distribution of the data to be transmitted in the form of digital elements in the time-frequency space and the transmission of symbols each formed by a multiplex of N orthogonal carriers modulated by a set of the digital elements, and transmitted simultaneously, the device including channel encoding means comprising at least two types of modulation and/or at least two encoding efficiency levels. This enables to optimize the use of the transmission channel by assigning differentiated transmission techniques to portions of data of a same digital train as a function of the different levels of protection sought, against transmission errors.

Abstract: A synchronization system for locking a data input signal to a local clock uses the data input signal to provide the timing for capturing phase waveforms generated by a delay element string and a local oscillator. A transition detector generates bit patterns which correspond to a captured phase waveform which is in synch with the data input signal. The bit pattern of the captured in synch waveform is stored in a storage device under control of window detection and control logic also timed by the data input signal. The control logic stores a new bit pattern of a new phase waveform when the window detection logic determines that the new bit pattern is outside a 2-bit window and then selects the new phase waveform correponding to the new bit pattern for clocking the data input signal if the new bit pattern hasn't changed after N consecutive cycles of the data input signal.

Abstract: System and method for determining an absolute phase value of a differentially-encoded, DQPSK signal. A stored set of sequences of an ID sequence is compared with a received ID-sequence of a differentially-encoded, DQPSK signal transmitted to the receiver. The stored and the received ID sequences are correlated, and the stored values of the ID sequence are adjusted by the value of the calculated correlation.

Abstract: A novel receiver for subcarriers in a radio broadcasting system is described, in which the characteristic frequency of the mixing oscillator is varied under program control. An incoming signal from antenna 1 passes through an input stage 2 to a mixing stage 3. Mixing stage 3 receives the output of an oscillator 4. The output of the mixing stage passes into an intermediate frequency filter stage 5, which preferably includes A/D converters 13 and demultiplexers 14. Stage 5 feeds a plurality of demodulators 6, which may include equalizers 12. Buffer memories 7 store information from demodulated subcarrier signals, and feed an evaluation unit 8. Evaluation unit 8 has a first output which drives a speaker 9 and a second output which is applied to a memory 11. A control unit 10, connected to the output of memory 11, controls the frequency generated by mixing oscillator 4.

Abstract: A switching system exchanges communication information as fixed length cells between a plurality of incoming and outgoing highways. The fixed length cells each have a plurality of data portions with one data portion designated as a header portion for containing switching information. An address generating circuit generates read addresses and write addresses in response to the header portion of each cell and a control circuit. The plurality of cells from the incoming highways are simultaneously rotated in a rotation matrix with each of the cell's data portions rotated to a unique internal path. The data portions are then transmitted to identical write addresses in a plurality of memories via delay circuitry. The write addresses are transmitted through shift registers to the plurality of memories to allow the data portions of a single cell to occupy identical addresses within a plurality of memories.

Abstract: A data transmission system receiver is disclosed which receives a formatted data stream (302) and operates in one of at least a first bandwidth mode and a second bandwidth mode. The formatted data stream (302) comprises a plurality of data edges (108, 110) and is sampled by a first clock signal (320). A plurality of clock edges (102, 104) defining transitions from one logic state to another is used to define "early" and "late" data edge occurrences. These occurrences are accumulated in accumulators (310, 312) and used as inputs to a clock counter (318) which produces a phase-adjusted clock signal (320). Additionally, the data transmission receiver comprises a detector (330) for detecting when a limited data stream (306) is synchronized with the phase-adjusted clock signal (320) and, in accordance with a predetermined algorithm, is able to switch the phase-lock circuit from the first bandwidth mode to the second bandwidth mode.

Abstract: Broadcasting system digitizes audio input signals before RF modulating and transmitting over airwaves to one or more remote receiving stations. Receiving station recovers the digitized signal by demodulating and exponentially expanding the received RF signal. Recovered digital signal is subsequently frequency modulated and sent, via an electrically conductive cable, to an FM radio, over which the original audio input signals are faithfully reproduced. A time switch in series with the RF receiver and the FM modulator is capable of temporarily disabling modulated transmissions to radio through the electrically conductive cable. Relay stations, (either land-based or satellite), allow for transmission beyond the range (i.e. "line-of-sight") of common FM radio transmissions.

Abstract: Multirate wire line modem apparatus operable at either of two rates in either transmission or reception modes is provided according to the teachings of the instant invention. Full duplex operation and echo cancellation are utilized for both voice and data. Structurally an IOP processor acts as a system controller in controlling transmission and reception digital signal processors which provide the independent transmission and reception functions of the resulting multirate modem apparatus.

Abstract: A communication control unit controls data transmission and reception between a terminal and a communication network which includes a full duplex communication path, and a communication is made by transmitting a sending signal which includes a destination address of a destination terminal and transmitting a returning signal when the destination address is confirmed.