Abstract: A multi-mode gain control loop for a PR4, ML data channel, such as one included in a magnetic disk data storage device, includes an input for receiving from a source an analog signal stream including coded data to be detected; a VGA for amplifying the analog signal stream; an analog to digital converter for receiving the analog signal stream and for generating and putting out data samples therefrom; an analog gain control loop connected to generate an analog gain control from the analog data stream during a data non-read mode of the channel, to store the analog gain control in a storage circuit, and to apply the stored analog gain control constantly to control the VGA; and a digital gain control loop connected to generate gain vernier correction values from the data samples and for applying the gain vernier correction values through a gain DAC to provide an offset control to the VGA during a data read mode of the channel.

Abstract: It is intended to converge parameters stably in a short time upon automatic adjustment of parameters of a bit identifier by which a signal reproduced from a magnetic recording medium and equalized by the Nyquist standard is compared with a threshold value and converted into a binary signal. An estimation value H(j) of an equalization error is cleared in step 1. Such estimation values H(j) are added in step 2 without being limited in the number of occurrences of addition. A result of the addition is compared with a converging coefficient M in step 3. As long as the result of the addition does not exceed the converging coefficient M, addition is repeated. When the result of the addition reaches the predetermined value, a fixed step .DELTA. is added to or subtracted from a parameter in response to the estimation value H(j). Therefore, parameter renewal interval is variable in response to the amount of equalization errors.

Abstract: A local area network station (12) includes a transceiver (20) adapted to transmit and receive signals over a wireless communications link. The transceiver (20) is coupled to a CSMA/CD LAN controller device (22) and to a signal generator circuit (40) which is also coupled to the LAN controller device (22). If the station (12) desires to transmit a data frame but a carrier sense signal (CRS) indicates that the link is busy, transmission of the data frame is deferred, and after the carrier sense signal (CRS) becomes inactive, a collision is simulated by the signal generator circuit (40) providing a CDT signal to the LAN controller device (22) which goes into a backoff mode and attempts to retransmit the frame after a random backoff time. Thus, commercially available CSMA/CD chips can be utilized in a single wireless channel LAN environment using a CSMA/CA protocol, with a low risk of collisions.

Abstract: Method for setting the asynchronous transmission characteristics in a telecommunication equipment including a Serial Communication Controller (SCC) operating at different transmission rates, parity modes and numbers of bit per character. The method according to the present invention involves the step of setting the SCC at the higher communication rate in a none parity mode with a number of 8 bits per character. There is received a predetermined sequence of characters consisting in a succession of "Carriage Return" (CR) and "." characters. The method further involves the step of processing at least three received characters (CR, ., CR) involving the step of analyzing said received characters by comparing them with predetermined values simultaneous with the detection of parity errors, the processing step further involving the step of setting in responsive to the analyzing step, the SCC with the actual number of bits per character and the real parity mode which is used in the asynchronous transmission.

Abstract: A circuit for developing a binary bitstream signal from a ternary analog signal having positive and negative amplitude peaks includes an analog-to-digital converter for receiving the analog signal and providing digital samples in accordance with the amplitude and polarity of the analog signal. The most significant bit of digital sample indicates the polarity of an analog signal sample. A threshold value is compared to a current amplitude sample to indicate a level change in the analog signal when the sample value exceeds the threshold value and the polarity differs from that of the preceding sample which exceeded the threshold value. The current sample value which exceeds the threshold value is compared with preceding sample values which exceeded the threshold value, and a level change is indicated by the sample value which most exceeds the threshold value. Incorrect sample values are inverted in a correction circuit.

Abstract: A three frequency system employs frequency shift keying (FSK) to transmit digital data from a plurality of non-stationary objects such as fuel trucks connectable to a plurality of transmit locations such as fuel pumps in a hazardous environment to a "safe area" computer. The three different frequencies are transmitted respectively as three pulses of different frequencies.

Abstract: A method and device for receiving data in a synchronous communication system. Data can be accurately transferred between two subsystems in a synchronous system even where the clock skew and propagation delay between the two subsystems is unlimited. The receiving subsystem is initialized to ensure synchronous data transfer over a theoretically infinite range. The transmitting subsystem transmits data and a forwarded clock to the receiving subsystem. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the clock of the receiving subsystem by controlling a multiplexer which selects the proper state device output to pass to another state device for alignment to the receiving subsystem's clock. The multiplexer is controlled by a circuit which monitors the capturing of the incoming data and determines the correct state device output to select for proper data alignment.

Abstract: A channel coding system comprising apparatuses and methods for encoding and decoding signals is disclosed. The system utilizes an orthonormal basis of numerical sequences for coding an input signal. The orthonormal bases reduce channel interference. A method for generating long basis sequences from the product of shorter sequences is also disclosed.

Abstract: A new digital oscillator is described that can be synchronized with a broadcast digital input signal by iteratively rotating the phase of the complex oscillator signal by increasing or decreasing the components, depending upon the phase difference between the broadcast signal and the oscillator output signal.

Abstract: A transmitter suitable for ISDN use feeds the 2B1Q transmit signals directly into a sigma-delta modulator. The input word is two or three bits and the datapath within the sigma-delta modulator need be only six bits wide. The sigma-delta modulator has sample-hold means which has some filtering effect. The additional filtering requirements are met with an analog filter. No digital interpolation filter is required.

Abstract: A digital programmable loop filter for high frequency control systems applications utilizing a serial processing technique on pulse densities. The loop filter contains a proportional signal path and an integral signal path. A 4-time-slot sequencer time-multiplexes the serial proportional and integral signals to emulate a 1-pole/1-zero filter. An acquisition speed control circuit controls the acquisition time as well as step sizes of the scaler (proportional path) and the integrator (integral path) to provide loop variable programmability.

Abstract: A Bayesian blind equalizer which approximates the optimum symbol-by-symbol detector for an unknown intersymbol interference pattern in a communication channel is provided in a plurality of parallel processors. Each processor operates in parallel from a common data bus with each of the other processors. Each of the processors in turn generates an estimated signal and updated metric for the communication channel for a corresponding one of each of the possible data subsequences which could cause intersymbol interference. The estimated signals or innovations are then combined with the updated metrics in a supervisory processor to generate unconditional channel coefficients for the next received data sample. Using the estimated channel coefficients and received data samples, the transmitted data sample is reliably decoded notwithstanding intersymbol interference without the use of data preambles or training data and notwithstanding that the channel coefficients may be rapidly varying.

Abstract: This device in which the elements are linked by two information transmission lines (2, 3) and each of which includes information sending and reception circuits (4, 5), linked to a protocol handler (6), is characterized in that the reception circuit (5) of each element (1) comprise three comparators (7, 8, 9), a first comparator (7) receiving the signals transiting on the two lines (2, 3), a second comparator (8) receiving the signals transiting on a line (2) and a third comparator (9) receiving the signals transiting on the other line (3) and, interposed between the output of these comparators (7, 8, 9) and the information input (RC) of the handler (6), a circuit (10) for selective connection of the output (R0) of the first comparator (7) or of the output of a circuit for logically combining the outputs (R1, R2) of the second and third comparators (8, 9), to the input of the protocol handler (6), under the control of the latter as a function of the state of the signals present at its input, in order to permit

Abstract: In a QAM communications system, a novel synchronizing sequence of symbols added to the information channel simplifies acquisition of timing and synchronization by a receiver. Such synchronization vectors provide signals for improved AFC control signal generation.

Abstract: In an apparatus for executing an algorithm for realizing an orthogonal transform operation such as the 8 points fast cosine transform, by operating on successive sets of data values of a digital signal such as a digital video signal in such applications as high efficiency coding of a digital video signal, a plurality of multiplication operations that are executed during processing of each set of data values are executed sequentially by time division multiplex operation of a single multiplier (32) which is capable of executing a multiplication operation within one sample period of the digital signal, with input and output data values being transferred by selector units (11, 33, 41) between the multiplier and other sections of the apparatus at appropriate times during processing of each set of the input digital signal values. The scale of hardware required for the apparatus is thereby reduced by comparison with an apparatus which employs a plurality of separate multipliers.

Abstract: Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous digital signal, e.g., a DS3 signal, from a received synchronous digital signal, e.g., a SONET STS-1 signal. The improved jitter performance results from the use of a unique dynamic bit leaking arrangement in conjunction with a digital phase locked loop and desynchronizing elastic store. An optimum bit leak interval is obtained by controllably leaking a greater number of shorter interval STS-1 bits than the number of received pointer adjustment bits or, alternatively, leaking a fewer number of longer interval bits than the net number of received pointer adjustment bits. Additionally, the affect of random pointer adjustments and the superposition of randomly received pointer adjustments on a periodic sequence of received pointer adjustments is minimized by employing a "static" queue of pointer adjustment bits to be leaked.

Abstract: A digital data generation system including a programmable dominance RS flip-flop has a random access memory that stores a user selected sequence of test data. A pattern formatting logic circuit receives the test data and produces, for each data period, a coarsely timed candidate pulse for identifying the leading edge of an output data pulse and a coarsely timed candidate pulse for identifying the trailing edge of the output data pulse. A precision delay circuit finely tunes the timing of the candidate pulses. The finely tuned pulses are applied to an RS flip-flop circuit which can be programmed for set or reset dominance, thereby preventing an indeterminate state when a logic "1" is applied to both the set and the reset input. In the system, the flip-flop is programmed so that the most recent of the lead pulse or the trail pulse prevails.

Abstract: A process and a circuit for carrying out the process for adapting coefficients in a modem equalizer comprises a memory cell for storing a coefficient, an adapter receiving the output of the cell and providing a first signal having a first correction, and an adder receiving the first signal and providing a second signal to the cell. The adder also receives a value k much smaller than 1 having the sign provided by a comparator comparing an initial value of the considered coefficient and its current value.

Abstract: A method and an apparatus for converting a frame phase of a signal having a frame structure specified in the CCITT recommendations which contains N (N: an integer 2 or above) pieces of frames applied with time-division/multiplex, in which the N pieces of frames are given to N pieces of memories, respectively, a write address is given independently to each memory so that the N pieces of frames are written in the respective memories in a same phase as the phase in the signal, a read address is given independently to each memory so that the N pieces of frames are read out of the respective memories in a same phase as the write phase, a difference between a write address and a read address in each memory is set identical under an initial state, and justification is executed for a frame which is read out of the memory in accordance with a difference between existing write address and read address in each memory, whereby to perform frame phase conversion while maintaining relative phase among respective frames.

Abstract: An automatic detection and selection circuit resident in a DCE is provided. The circuit is coupled to the DCE interface connector and detects receipt by the DCE of V.35 and RS-232 transmit data signals, distinguishes between those signals, and selects circuitry for passing the data therethrough. The circuit comprises a switch coupled to a first TX data terminal (pin 2 or P) of the DCE interface connector, first and second line receiving circuits, a microprocessor, and a relay. The first line receiving circuit is coupled to a first pole of the switch and to the second TX data terminal (pin S) of the DCE interface connector and provides indications as to whether or not an input signal is present at at least one of pins P and S. The second line receiving circuit is coupled to the second pole of the switch and provides indications as to whether or not a valid RS-232 transmit data signal is detected.