Abstract: Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous digital signal, e.g., a DS3 signal, from a received synchronous digital signal, e.g., a SONET STS-1 signal. The improved jitter performance results from the use of a unique dynamic bit leaking arrangement in conjunction with a digital phase locked loop and desynchronizing elastic store. An optimum bit leak interval is obtained by controllably leaking a greater number of shorter interval STS-1 bits than the number of received pointer adjustment bits. Additionally, the affect of random pointer adjustments and the superposition of randomly received pointer adjustments on a periodic sequence of received pointer adjustments is minimized by employing a "static" queue of pointer adjustment bits to be leaked. The queue is dynamically maintained at its "static" count so that there are always bits in the queue to be leaked at the desired optimum bit leak interval even in the presence of randomly received pointer adjustments.

Abstract: A system and method for fourier transform coding of data on peak limited channels using a redundancy scheme. The system and method section the data to be transmitted into contiguous blocks having sequence lengths of 2N. Each block is coded in the frequency domain and its Inverse Discrete Fourier Transform (IDFT) for each coded block is computed. The IDFT blocks are then clipped at predetermined peak values .+-. P to thereby derive clipping error values. The magnitude of the clipping error values is then determined. The magnitude squared values of the clipping error is summed for each block. If the sum exceeds a threshold .phi. for a given block, then, the block is transmitted X number of times, where X is a fixed number, each time using less than the prescribed power for the transmission, otherwise, a continuous signal is transmitted whose sampled values at the Nyquist rate are the clipped values of the IDFT for that particular block.

Abstract: A signal detection apparatus detects original information from a PCM signal transmitted through a communication channel or reproduced from a recording medium. The apparatus includes: a first equalizer for equalizing the PCM signal so as to decrease intersymbol interference, a clock regenerator for regenerating a clock signal synchronized with a timing of the digital information from an output of the first equalizer; an amplitude detector for detecting an amplitude from the output of the first equalizer and the clock signal; a second equalizer for equalizing the output of the first equalizer to a partial-response equalized signal, and a detecting circuit for detecting the original digital information at a clock timing of the clock signal from the partial-response equalized signal. Accordingly, without being influenced by the amplitude fluctuations of the signal, the original digital information can be detected at a low bit error rate.

Abstract: A transmitter is provided with a distribution preserving Tomlinson coder which predistorts shaped data signals such that the power of each data signal exiting the coder is substantially similar to the power of the data signal entering the coder and such that upon transmission of the predistorted data signal over a channel, the effect of ISI of the channel is substantially removed. The transmitter is primarily intended for coded modulation systems utilizing a "coset" code, and the predistortion is preferably accomplished according to a linear function ##EQU1## where r.sub.k is a data signal entering the coder, a.sub.l and b.sub.l are the coefficients of polynomials relating to the channel impulse response, x.sub.k is the predistorted data signal exiting the coder, and s.sub.k is a multiple of a given value (N) which is chosen to cause x.sub.k and r.sub.k to occupy identical defined regions in space, where the total length of each defined region is the given value N.

Abstract: A frame synchronization dependent type bit synchronization extraction circuit in an ISDN terminal equipment connected to a reference point S/T of an ISDN basic user network interface, for establishing bit synchronization between an internally produced signal and received data. To make the timing extraction jitter small and make the bit timing stable, it comprises a counter preset mode synchronization unit, a digital phase-lock loop mode synchronization unit, frame synchronization detection unit, and an inhibiting unit for inhibiting the operation of the counter preset mode synchronization unit, and the bit synchronization is effected by only the digital phase locked loop mode synchronization unit after the frame synchronization is detected by the frame synchronization detection unit.

Abstract: A data transmission system and method in which digitalized information is transmitted via a data transmission link in complete binary words from a transmitter to a receiver. For data transmission, a complete binary word with a defined total bit number is subdivided into one or more partial binary words, with the respective bit numbers of the partial binary words being variable. The individual partial binary words are allocated all binary bit sequences that can be formed with the total number bits of the respective partial binary words, the various bit sequences being coded at respectively different positions within a partial binary word In each partial binary word exactly one binary bit sequence is transmitted from the transmitter to the receiver.

Abstract: Apparatus useful for communicating digital data using a steady stream of pulses which achieve very high ratios of bit rate per occupied bandwidth using digital signal synthesis techniques to produce a stream of constant phase tone pulses having exceptional spectral compactness. An optimal pulse is formed having either no sidelobe energy in the frequency spectrum and few to no sidelobes in the time domain, or no sidelobes in the time domain and minimal sidelobe energy in the frequency spectrum. Each optimal pulse has a specially shaped, non-constant amplitude envelope. The embodiment having no sidelobes in the time domain uses both a pulse envelope corresponding to a Dolph-Chebychev function and more than one frequency of tones with offset timing of overlapping tone pulses so that their envelopes go to zero at different times. The invention is particularly well suited for single sideband radio communication at frequencies below 30 MHz.

Abstract: An equalization system for equalizing a corrupted signal is disclosed. The equalization system includes a complex matched filter (400) and a maximum likelihood sequence estimator (MLSE) (405) for removing the effects of phase shift, amplitude variations, intersymbol interference, etc. resulting from multi-pathing and noise contributed by the receiver front end. The system estimates a correlation signal C(t) (505) and synchronizes C(t) 505 to maximize its energy as seen on the taps of the complex matched filter (400). Taps having amplitude coefficients below a predetermined threshold are set to zero to produce a modified CIR estimate. The modified CIR estimate which has had the effects of noise virtually eliminated, is then used to construct the complex matched filter (400) and is also used as input to the MLSE (405) to produce a better equalized data signal.

Abstract: A system for controlling for gain and phase errors due to mismatches between signal channels in direct conversion receiver having a pair of signal channels carrying I and Q baseband component signals which are in quadrature. In accordance with the system new I' and Q' signals are generated which may be viewed as analogs of the I and Q baseband components but which are related to twice the phase angle defined by the original I and Q baseboard components signal components. Phase angles are determined based on the original I and Q baseband components signals and the new I' and Q' signals. An error signal is then formed from these signals which can be analyzed to determine the gain and phase errors affecting the I and Q baseband components. These components can then be adjusted to correct for gain and phase errors in order to compensate for hardware mismatches between the signal channels in the receiver.

Abstract: A time division PLL is composed of a complex multiplier (1), a phase difference detector (2), a low-pass filter (3), an adder (4) and a digital VCO (5). A D.C. value indicating the recovered carrier component of a receive burst is obtained by a squaring circuit (9) from a baseband signal, which is the output of the complex multiplier (1). The time division PLL operates as a PLL having frequency different lead-in ranges on a time division basis, differing between the period in which no burst has been received yet and the period in which the former part of the carrier recovery section of the receive burst is being received. It operates, from the latter part of the carrier recovery section until the completion of data reception, as a PLL having the frequency pull-in range in which the greatest D.C. value was outputted during the time division operation.

Abstract: An automatic equalizer for a data transmission channel capable of removing intersymbol interference and phase fluctuations accurately without lowering the convergence rate even when the frequency characteristic of the channel sharply changes. A summation output to be fed to a decision unit has the phase thereof so rotated as to compensate for an amount of phase fluctuation. The output of the decision unit to be applied to a feedback filter, which follows the decision unit, and an error to be applied to a tap coefficient control section each has the phase thereof rotated in such a manner as to add phase rotation in matching relation to the amount of phase rotation. Even when the tap coefficient control section is implemented with an RLS (Recursive Least Square) alogorithm, it can update tap coefficients by the same procedure with no regard to phase fluctuations.

Abstract: A process and a device transmits numerical data in the form of a sequence of words. The process includes an encoding phase, a transmission stage and a decoding phase. In the encoding phase, the data creates an analog signal whose period is composed of several fractions of the period, each one depending on a word of the data. The analog signal is transmitted. In the decoding phase, the signal is divided into p fractions corresponding to the encoding fractions, and the fractions are analyzed to deduce the sequence of words. The process permits a high flow of transmission for a particular transmission band width.

Abstract: A transmission media driving system for receiving high data rate serial binary data signal, dividing the signal into two or more lower data rate signal paths, modified duobinary encoding the signals and transmitting the signals on respective two-conductor transmission lines. The system includes ample encoding circuits for generating control signals and a line driver circuit, associated with each encoding circuit, that is responsive to the control signals to drive one of the transmission lines with the modified duobinary encoded signal through a transformer. The driver circuit includes multiple current sources that are switched to conducting or nonconducting states in response to the control signals to drive currents through a primary winding of the transformer to achieve appropriate levels of the encoded signal.

Abstract: Subblocks of input digital samples are stored into a buffer at frame intervals and segmented into blocks having an integral multiple of the length of the subblock. Each block is encoded into transform coefficients and stored into a memory. Each coefficient is squared and those of the squared transform coefficients which correspond to high-frequency components of the input digital samples are summed and a minimum value is detected therefrom as corresponding to an optimum block length. Those transform coefficients which correspond to the optimum block length are selected from the memory and multiplexed with a signal representative of the optimum block length. In a modification, interblock differences are detected between successive transform coefficients of equal block length and squared. Those of the squared interblock differences which correspond to equal block length are summed, producing a set of squared sums for each block length.

Abstract: The present invention provides a phase detector comprising a driver U1 and D-type flip-flops U2 and U3 which reduces the high frequency component of the jitter in VCO, in analog-fashion operation, enables the use of general purpose logic elements being irrespective of the data bit speed, and enables the application of both analog PLL and digital PLL.

Abstract: A communications stimulation system allows a user to perform a quantitative or subjective test of digital baseband devices over wireless channels using actual measured or modeled propagation data. The digital wireless communication simulation system is capable of simulating the transient nature of channels and radio hardware so that loss of synchronization can be included in the simulation. The simulator is a combination of computer software and hardware that computes a convolution, in the time domain, of a sequence of binary digits or data symbols (i.e., the data stream) with a computer model of a radio transmitter, a propagation channel or channels and a receiver. The transmitter typically comprises a coder, a pulse shaper, a modulator, and a spreader. The propagation channel or channels may include impulsive and average noise levels, co-channel interference and adjacent interference levels, fading and multipath propagation events, and non-linear channel and radio system effects.

Abstract: An automatic gain control circuit (AGC) in a receiver for a digital radio telephone. Most of the total gain control of the received signal is accomplished in the base band frequency sections, i.e. in the I and Q branches, where the signal amplification is controlled step by step, and only a minor part of the total gain control is performed in the RF stage. High amplification steps are formed with amplifiers (9a, 10a, 11a, 12a; 9b, 10b, 11b, 12b), wherein the desired amplifier is activated with a digitally controlled (A, B) multiplexer (13a, 13b), and low amplification steps are formed with a resistance attenuator (14a, 14b), in which a signal of desired level is selected by a digitally controlled (C, D, E) multiplexer (15a, 15b). In addition, the RF amplifier (2) has two amplification levels and the desired amplification is selected with a digital control (F). With the different digital control combinations (A, B, C, D, E, F) the entire gain control range required of the receiver can be covered.

Abstract: The present invention provides a method of estimating parameters of a mobile radio channel which are used for providing the equalization and synchronization of the radio channel. The channel is modelled as a discrete number of independent Rayleigh-faded propagation paths. First, the relative delay of each path is estimated, using maximum likelihood methods. Using this information, the associated time-varying path weights are then determined using a least-squares fit. This is sufficient information to estimate the impulse response of the channel. The actual equalizer weights are then obtained by inverting the estimated channel impulse response.

Abstract: There is provided a digital signal reproducing apparatus comprising: a binarization circuit to binarize a signal which was read out of a recording medium or a transmitted signal; first and second pulse generators to generate pulses which are respectively synchronized with leading and trailing edges of a binary signal which was binarized by the binarization circuit; and first and second signal generators to generate first and second position signals indicative of the positions of the leading and trailing edges synchronously with the first and second sync pulses which are generated from the first and second pulse, generators. The binary signal is a signal of the NRZI coding method. Each pulse generator has a PLL circuit. With the apparatus, the signal can be accurately reproduced irrespective of the recording density by compensating the phase difference between the leading and trailing edges of the binary signal.

Abstract: In a network termination connected to an exchanger and a plurality of terminal adaptors, and enabling relief of call congestion in an exchanger, the network termination includes: a reception port for receiving a reduction rate indicated by a congestion information area in a SDH frame input from the exchanger; a SDH frame transmission unit for transferring the SDH frame including a plurality of ATM cells, each ATM cell having a header field and an information field, and the header field having a busy bit field; an unusable cell preparation unit operatively connected to the SDH frame transmission unit for generating the ATM cell train including the unusable cells defined based on the reduction rate from the exchanger; and a transmission port operatively connected to the unusable cell preparation unit for transferring the ATM cell train including the unusable cells to the end terminals.