Abstract: A circuit, including a state machine, e. g. a logic array and a set of controlled storage devices, receives conditioning signals, such as reset, power failure signals and signals fed back from the storage devices, and uses the signals to determine which of a number of clock sources is to be used in a system. The state machine provides output signals which are processed by a delay circuit to ensure that switches between clock sources only occur during an inactive period of the clock signals to prevent signal glitches. The circuit's output signal controls a number of AND gates, each of which gates a particular clock signal to an output line. When a power fail condition occurs, a switch between a first clock signal and a substantially lower frequency clock signal is required to conserve power.

Abstract: A method of generating a composite signal in the form of a QPSK signal on which an additional carrier signal is superposed, wherein a carrier signal is conducted through two series connected, switchable phase shifters. One of the phase shifters is controlled by one of two data signals. Both data signals are logically linked with one another by a logic circuit, and the resulting linkage signal used to control the other phase shifter. The phase states into which each phase shifter can be switched are selected and the linkage signal formed from the data signals such that, with the available values of the data signals, the carrier signal passing through the phase shifters is brought into the phase positions that should exist with the additional carrier signal superposed.

Abstract: A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal.

Abstract: Voltage controlled oscillator 40 has an oscillation stoppage cancelling circuit 46 and a current/frequency converter circuit 44 which is a ring oscillator made by connecting inverters forming 3 stages like a ring. Oscillation stoppage canceling circuit 46 stops and releases oscillation of the ring oscillator by a control signal RS. One-shot circuit 3 has a pulse width adjusting circuit 60 which is made by cascade-connecting the inverters constituting the ring oscillator of current/frequency converter 44 and inverters having the same characteristics in 3 stages. When the PLL enters a synchronization field, a synchronization field detector 1 issues a detection signal C and an input switch signal SC; a selector circuit 2 selects read data; and oscillation control signal RS starts upon the rise of a pulse S.sub.IN. Oscillation stoppage cancelling circuit 46 thus stops oscillator 40 and keeps an output V.sub.OUT at H level.

Abstract: A differential line driver with small common mode shift when going inactive. Two pairs of serially coupled switches diagonally switch when sending data. All switches close when the driver is disabled, the common mode output voltage being established by resistors serially disposed between the pairs of switches and the power source therefore.

Abstract: A method and apparatus for controlling an equalizer receiving the output of an unknown system in order to produce a desired response for recovering the input to the system are characterized by iteratively adjusting the equalizer such that the unknown system combined with the equalizer behaves essentially as a linear system whose (t,n) taps, for some combinations of t and n, are iteratively adjusted according to the following rule: ##EQU1## where s.sub.t,n denotes the (t,n) tap before the iteration, s'.sub.t,n denotes the (t,n) tap after the iteration, I is a preselected integer greater then or equal to one, .alpha..sub.i i=1,2 . . . I are preselected scalars that may vary from iteration to iteration, and p.sub.i, q.sub.i i=1,2, . . . I are preselected non-negative integers such that p.sub.i +q.sub.i .gtoreq.2.

Abstract: A digital radio receiver for synchronization of radiowave transmissions for digital and analog FM signals in TDMA systems such as cellular telephones uses a tangent type differential detector that minimizes the bit error rate. The differential detector employs an A/D converter circuit that samples a received signal, a sorter circuit that selects a predetermined number of samples to be used in the decoding, a sample and phase adjustment circuit that allows for a carrier phase adjustment and sample timing adjustment, a divider circuit that eliminates the need for a conventional limiter by causing a ratio of amplitudes to be processed instead of absolute signal amplitudes, an inverse tangent circuit creates a decoded phase angle from the ratio, a delay circuit and a summer circuit that create a differential signal, a modulo-2.pi. correction circuit that corrects for wrap-around errors about the real axis, and a four-phase decoder circuit to decode the signal into a pair of bits.

Abstract: Bit synchronization is achieved by identifying potential bit sample points and assigning corresponding weight values as a function of signal noise vulnerability. The greater the possibility of error due to signal noise, the smaller the assigned weight value. The bit sample points associated with the largest accumulated weight value are taken as the appropriate data sample points for extracting information from the data signal. For a duobinary signal, zero crossings are identified as potential bit sample points and assigned a weight value corresponding to signal slope thereat. The number of possible bit sample points associated with each actual bit sample point is limited to a finite set by phase locking the carrier signal to the data rate.

Abstract: A circuit architecture suitable for use in a television receiver which effectively performs a ghost or echo cancellation procedure on post echo components and pre echo components occurring within the transmission channel. The apparatus features a filter circuit architecture which can be configured under programmed control so as to partition groups of its filter sections to form IIR filters and FIR filters. The filter architecture is suitable for use in multi-circuit configurations and can be used with clustering algorithms to increase the efficiency and optimize the use of the available circuit architecture.

Abstract: A method for reducing the phase noise introduced in the resynchronization of digital signals using positive, negative or positive-negative justification, in which a phase comparison signal representing the phase difference between signals from a local clock and a remote clock is generated, the comparison signal is modified by a suitable scale factor, the scaled phase comparison signal is integrated at a suitable frequency, the integrated signal is quantized by comparing the integrated signal with predetermined thresholds, and the transitions of the quantized signal are used to determine the justification events which are to be overlapped to a local unjustified clock rate to generate a local justified clock signal.

Abstract: A MUSE sound decoder detects a broadcasting/non-broadcasting identification flag included in the control signals in an applied MUSE signal to determine whether the MUSE signal is broadcasted or non-broadcasted. The MUSE sound decoder further includes a frame synchronization protection circuit for protecting frame synchronization over a predetermined frame synchronization protection time period when the frame synchronization pattern is not detected at the proper timing. The frame synchronization protection circuit sets the frame synchronization protection time period to a long time period when the MUSE signal is determined to be a broadcasted MUSE signal, and to a short time period when the MUSE signal is determined to be a non-broadcasted MUSE signal. Appropriate muting of a sound signal can be carried out according to the condition of the received MUSE signal.

Abstract: A clock recovery system for radio communication inserts a synchronization signal (102) at a frequency of 1/2 the baud rate, at the spectral null of an MSK data signal (108), which is also at 1/2 the baud rate, for later retrieval. Hence, in a transmitter-encoder (100), an MSK generator (106) generates an MSK digitally modulated data signal (108e) having a baud rate and a spectral null at 1/2 the baud rate. A synchronization clock generator (104) generates a synchronization signal (102e) having a frequency at 1/2 the baud rate. This frequency at 1/2 the baud rate corresponds to the spectral null of the MSK digitally modulated data signal (108e). A transmitter transmits the synchronization signal (102e), at the spectral null of the data signal (108e), together (112) with the MSK digitally modulated data signal (108e).

Abstract: An output resistance (R.sub.O) is situated at each output of a plurality of drivers communicating to a plurality of receivers via an interconnect network which is biased by a terminal supply voltage (V.sub.T). The output resistance R.sub.O eliminates the need for a wait period in a cycle, which wait period is usually required when mastership of the interconnect network changes over from one driver to another driver. The drivers and receivers are two-state devices. For a logic high, the drivers exhibit a virtually infinite resistance. Consequently, the interconnect network exhibits a high voltage V.sub.INT, which is approximately equal to the terminal supply voltage V.sub.T. Whereas for a logic low, the drivers sink current from the interconnect network, thereby pulling the interconnect network voltage V.sub.INT towards ground. Any signal below about (7/8)*V.sub.T is recognized by the receivers as a logic low, while any signal above this threshold is recognized as a logic high.

Abstract: A sequence estimator for estimating a data sequence which is to be transmitted using a Viterbi processor, includes a register for storing, at a predetermined time interval, signals applied to the sequence estimator. A channel impulse response calculator is provided to receive the signals stored in the register which determine an estimated channel impulse response of each of possible transmitted data sequences. The sequence estimator further includes a branch metric calculator which determines a plurality of branch metrics using the receive signal, the possible transmitted data sequence and the estimated channel impulse response.

Abstract: In a conventional case where a preamble length is adjusted in a communication network, even if there is a frame (cycle) in which the length of the preamble has already been adjusted by a preceding station in the direction in which it is increased or decreased, if it is determined on the basis of the decision conditions of an active station that the length of the preamble of such a frame should be increased or decreased, the length of the preamble is adjusted in the direction in which it is further increased or decreased. However, according to the present invention, the length of each preamble which is inputted to a buffer is monitored, and if it is determined that the preamble length of a frame has already been adjusted in the same increasing or decreasing direction, adjustment of the preamble length of the frame is inhibited and such adjustment is carried forward to a succeeding frame.

Abstract: A digital filter for a phase-locked loop operates to compare the bit values of the data represented by the incoming pulse stream with patterns in that pulse stream known to produce bit shifting (either early or late). The bit shift caused by physical interaction of bits encoded on computer diskettes or the like always is predictable, in accordance with the pattern of previous bits, the current bit and the next bit. This information is processed by a logic circuit to predict which pulses in the incoming stream of data pulses are shifted. A signal is produced each time a predicted shifted pulse is determined; and this signal is utilized in conjunction with the output of the phase difference counter in the digital phase-locked loop to permit the phase of the controlled oscillator to be adjusted at each unshifted bit in a normal manner, and compensated for adjustment in a modified manner as a result of the prediction of the shifted pulses.

Abstract: A digital phase detector circuit is designed for particular application with a phase-locked loop voltage controlled oscillator system for synchronizing the MFM synchronization pulses on a floppy disk with the operation of the computer in which the disk is used. A classical Type 4 digital phase detector is employed, to which a bistable latch is added. The latch is set upon coincidence of reference and data pulses applied to the phase detector within a pre-established time interval or window. The output of the phase detector then is utilized only when the output of the latch indicates such coincidence; so that erroneous control signals are not supplied through the loop whenever data pulses fail to occur in adjacent time frames or windows.

Abstract: A method for recognizing modulation of radioelectric transmissions from instantaneous spectra of transmission observed in a determined frequency band by a Fast Fourier Transform spectrum analyze is disclosed wherein the method involves the calculation of a plurality of parameters for each transmission spectrum line which is observed. The parameters include the calculation of a mean amplitude of all the lines k of the spectrum contained in the determined frequency band and the calculation of a signal-to-noise ratio as well as a standard deviation in amplitude of each line of the spectrum. Also calculated is a coefficient of correlation COR(k,k) of amplitude of each line k with the homologous lines of the transmission spectrum contained in the determined frequency band.

Abstract: An improved decision feedback equalizer for use with digital communications. The equalizer includes an error detector, a process controller, a parameter selector and a data buffer for temporarily storing a digital data signal received from a communication channel. The error detector determines whether the equalizer is accurately tracking changes in the communication channel's characteristics or is lost. When the error detector determines that the equalizer is lost, the process controller responsively generates control signals for initiating an optimal retraining/recovery method for the prevailing conditions. In some retraining/recovery methods, data is temporarily stored in the buffer. The stored data is later retrieved and processed once the equalizer is retrained. Retraining is performed using a retraining signal received via the communication channel or, if available, a portion of the data signal which is suitable for retraining, thereby permitting more rapid resumption of data reception.

Abstract: Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous signal, e.g., a CEPT-4 signal, from a received synchronous signal, e.g., a SDH STM-1 signal. The improved jitter performance results from employing a unique gap generator which causes gaps in a received data signal to be spread regularly in time, and allows for almost continuous control by numerical techniques of the phase of a smooth output clock being generated. Phase control is obtained by employing a filtered version of the difference between the actual number of data bits in the received digital signal and the expected nominal number.