Abstract: A family of extended Generalized Viterbi Algorithm (GVA) and Soft Output Viterbi Algorithm (SOVA) decoders is disclosed. In one embodiment structural aspects of a SOVA are used to develop a new implementation for a serial GVA. Another aspect of the invention provides a low complexity SOVA that generates a reliability measure for decoded information using a list output of the GVA. In a further aspect, reliability information from a SOVA is used to develop a low complexity GVA.

Abstract: A methodology and concomitant circuitry for smoothing delay sensitive traffic utilizes short term traffic forecasts and guarantees meeting a prespecified delay constraint. The pattern of incoming traffic is used to forecast estimates of future incoming data from the present and past incoming data. Corresponding to the estimate is a data rate for propagating stored data to produce a smoothed outgoing data rate, and the interval of time over which such a rate is used so as to satisfy the delay constraint. The estimation procedure is then re-invoked at the end to the time interval, which takes into account data arriving during the time interval, so as to determine the next succeeding data rate and a new time interval for propagating stored data.

Abstract: A method and apparatus for control of concurrent communication of analog information and digital information. In general terms, when the communication channel is viewed as a multi-dimensional space, the digital information signal is divided into symbols, and the symbols are mapped onto the signal space with a preset distance between them. The analog signal, generally limited in magnitude to less than half the distance separating the symbols, is converted to component signals and added (i.e., vector addition) to the symbols. The sum signal is then transmitted to the receiver where the symbols are detected and subtracted from the received signal to yield the analog signal components. The transmitted analog signal is recreated from those components. Both half-duplex and full-duplex operation is available in accordance with this invention. The illustrative embodiment includes a controller that is sensitive to input signals applied to the modem disclosed herein.

Abstract: A method for adaptively turning on or off a decision directed algorithm (DDA) is performed according to the convergence state of the data to be equalized in a blind equalization system for use in a digital communication receiver. Each quadrant of a two-dimensional plane having an I-axis and Q-axis is divided into two decision areas. Then, a sign pair of actual error estimation data is calculated with respect to each area. If the decision error of the received symbol data is calculated, it is determined whether the sign of the decision error coincides with that of the actual error estimation data. The DDA is performed with respect to the symbol data of which the sign coincides with each other to update the equalization coefficient. The method further reduces the number of decision areas for dividing the plane formed by the I-axis and Q-axis in which the symbol data is arranged, to permit faster convergence speed and to further suppress the ratio of the symbol error.

Abstract: A modulation circuit for a digital signal recorder includes first and second high-pass filters for removing the direct current component in the output of the coded I and Q channels and for converting a 4-levels signal into a 7-levels signal. Additionally, a carrier signal generator for generating a carrier signal, a modulator for performing quadrature amplitude and phase modulations on the outputs of first and second high-pass filters using the carrier signal, a pilot signal generator for generating a pilot signal and combining the pilot signal with the output of modulator and for outputting the result for transmission or recording are also provided.

Abstract: A method and system are disclosed for permitting selected command sequences to be processed by a modem during data transfer operations. A preselected escape character is designated and inserted into a data stream to be applied to a modem in order to identify a selected command sequence which follows. A termination character is inserted into the data stream following the selected command sequence. Upon detection of the preselected escape character, the selected command sequence is coupled to a command processor within the modem and processed. In applications in which the modem is coupled between a data processing system and a cellular telephone communication channel, the selected command sequence may be utilized to transmit communication channel parameter status queries to a cellular telephone associated with the modem. In this manner, the Received Signal Strength Indicator (RSSI), bit error rate, or other indications of communication channel status may be queried.

Abstract: A .pi./4 shifted DQPSK modulator includes a mapping/filtering circuit (6) equipped with a mapping function and filtering function. The mapping/filtering circuit (6) allows phase information which is obtained for each symbol to be shift-input to its shift register (61, 62, 63) and sequentially reads out filter-processed filter factor data corresponding to 256 samples initially stored in a factor memory circuit (7) and allows the filter factor data to be converted to numerical values based on position information corresponding to 10 symbols output in parallel manner from the shift register (61, 62, 63). According to this circuit (6), it is possible to obtain filtered mapping data MF. Therefore, the modulator has less number of gates of the filter and can be embodied with a very simplified compact circuit configuration.

Abstract: A method and system are disclosed for permitting selected command sequences to be processed by a modem during data transfer operations. A preselected escape character is designated and inserted into a data stream to be applied to a modem in order to identify a selected command sequence which follows. A termination character is inserted into the data stream following the selected command sequence. Upon detection of the preselected escape character, the selected command sequence is coupled to a command processor within the modem and processed. In applications in which the modem is coupled between a data processing system and a cellular telephone communication channel, the selected command sequence may be utilized to transmit communication channel parameter status queries to a cellular telephone associated with the modem. In this manner, the Received Signal Strength Indicator (RSSI), bit error rate, or other indications of communication channel status may be queried.

Abstract: A hardware-efficient data receiver in which the receiver digital baseband signal samples relate to the bits in the transmission signal. For each sample, a metric calculator calculates an input data element (metric) for the soft decision decoder in the receiver. The metric is a binary word of whose most significant bit (gross bit) indicates the most likely value (`0` or `1`) of a bit in the transmission signal. The other bits of the metric (reliability bits) express the reliability of this gross bit. The metric calculator has a monotonous transition function with equidistant steps between two extreme metric values (all metric bits are `0` or `1`). According to this transition function, the metric value varies as a function of the digital baseband signal sample value in a range bounded by two saturation values. The number of different sample values in this range, including the saturation values, is two to the power of an integer.

Abstract: A method for the compression of data applied to a system for the transmission of data in protocol data units between at least one emitter terminal and at least one receiver terminal. Each protocol data unit comprises a header field and a data field. A first sequence of N source protocol data units is associated with a second sequence of M protocol data units to be transmitted, M being smaller or equal to N. The data fields of the protocol data units transmitted comprise data that has been compressed (according to at least one compression algorithm). The data fields are then made up of data contained in the data fields that has been compressed, and also data allowing reconstruction of N source protocol data units.

Abstract: An EPR4 detector comprises a PR4 Viterbi detector and an EPR4 post-processor for improving estimated output sequence at an output of the PR4 Viterbi. The PR4 Viterbi detector produces digital estimates of coded digital information values into the channel in accordance with a path through a PR4 trellis and produces other path information relating to other paths through the PR4 trellis.

Abstract: A method and apparatus for single signal, multiple channel digital information transfer through pulses with time slot allocation. The apparatus consists of one or more transmitting devices and one or more receiving devices. Multiple source signals are each allocated a unique time slot between successive synchronization pulses. Digital signals from each source are converted to positive analog information spikes which are combined in their respective time slot with a negative reference spike of uniform magnitude to form an information pulse. The total signal, which consists of successive synchronization pulses interspersed with information pulses for each signal source, each within its allocated time slot, is transmitted to the receivers. Each receiving device extracts the maximum information spike values and the reference spike values for one or more of the signal sources.

Abstract: A blind equalization process (200) for an adaptive equalizer including a plurality of taps, each having a corresponding coefficient, is disclosed which comprises the following steps. Blind equalization (204) is performed on a subset of the coefficients in the adaptive equalizer. Then, if the coefficients have converged (206), a decision directed adaptive equalization process (220) is initiated.

Abstract: Apparatus and method for realizing a parallel implementation of run length coding. The system encodes control and data information into the respective link control and data streams and merges the same onto the communication link for transmission. In addition, the system separates link data information from control information upon receipt of the information stream and decodes the received link data and control information into the original information.

Abstract: In a radiotelephone network, processing steps previously applied to digital voice transmissions received by a regional radio transmitter/receiver but not applied to analog voice transmissions received by the transmitter/receiver are applied to such analog voice transmissions at the transmitter/receiver itself such that analog voice transmissions and digital voice transmissions may be transmitted identically between the regional radio transmitter/receiver and a regional switching center. In particular, a digital speech encoder/compressor and a corresponding digital speech decoder/decompressor (together referred to as a codec) provided at remote transmitter/receivers and the regional switching center are also provided at the regional radio transmitter/receiver so as to apply the same processing to analog voice transmissions received from the remote transmitter/receivers as is applied to digital voice transmissions at the remote transmitter/receivers.

Abstract: In a combining circuit comprising first and second frequency converting sections (20a, 20b) for frequency converting first and second received signals from two independent antennas (10a, 10b) under the control of a control circuit (30) into first and second frequency-converted signals, first and second preliminary amplifying sections (60a, 60b) preliminarily amplify the first and the second frequency-converted signals under the control of the control circuit (30) to produce first and second preliminary amplified signals having first and second output levels, respectively. The first and the second preliminary amplified signals have first and second noise power levels, respectively, which are equal to each other. First and second main amplifying sections (40a, 40b) mainly amplify the first and the second preliminary amplified signals by first and second amplification degrees in proportional to the first and the second output levels, respectively.

Abstract: A FIFO uses a fill indicator circuit to indicate a fill status and provide control signals to a data source and data sink to cease operation. A serial string of FIFO cells propagates data from input to output by sending request and acknowledge signals between adjacent cells. The request signal initiates data transfer to the next logical cell and the acknowledge signal indicates completion of the transfer. The fill indicator has one cell for each FIFO cell for monitoring the request and acknowledge signals looking for predetermined state sequences to indicate whether each FIFO cell is full or empty.

Abstract: A serial data transmission device has a master unit, plural terminal units, and an abnormal detection unit connected by a signal line. Each terminal unit has an allocated address. The master unit interchanges data with each one of the plural terminal units in sequence. Each interchange of data with one terminal unit constitutes a cycle. Each terminal unit counts the number of data cycles of the master unit. When a terminal unit detects its assigned cycle number in the total sequence of cycles, a confirmation signal is output to the signal line. The abnormal detection unit determines the presence and location of an abnormality in accordance with the absence of a confirmation signal from a particular terminal.

Abstract: A phase detector 10 is disclosed herein. A clock signal CLK (OR I), a marker signal MARK (or Q) and a data signal D are provided. The data signal may comprise a periodic clock signal. Sampler circuitry 50 receives the clock signal CLK, the marker signal MARK and the data signal D and generates a sampled clock signal and a sampled marker signal. Sign modifier circuitry 52 then receives the sampled clock signal and sampled marker signal and generates first and second command signals. Select circuitry 54 receiving these command signals selects a valid command signal based upon the data signal.

Abstract: A frequency diversity communication system is provided whereby the number of hopping channels is reduced and a more continuous communication achieved as a mobile station travels from cell to cell by the combination of chips of symbols from the mobile sources. The transmitter divides each symbol of an input symbol sequence into a number K of chips, which are modulated with mutually different carrier frequencies. The receiver demodulates the signal sent by the transmitter by local frequencies corresponding respectively to the K different carrier frequencies. According to this invention, the carrier phase is coherent for each frequency of the received wave. Moreover, because the carrier phase is coherent, the outputs for each frequency of the received wave can be combined with the use of a training signal. The receiver also performs an estimation of the maximum likelihood of the transmitted symbol to eliminate the need for decoding.