Abstract: A pulse width modulator (PWM) (20) receives a two's complement input number and separates a sign bit from remaining less significant bits. The PWM converts these bits into an unsigned number in dependence on the sign bit. A comparator (41) provides a compare output signal in response to an output of a counter (30) equaling the unsigned number. An output circuit (25) provides first and second pulse width modulated signals for a length of time determined by the output of the comparator (41) in dependence on whether the sign bit indicates a positive or negative sign. In one embodiment, the PWM (20) converts a negative two's complement number to the unsigned number by one's complementing the least significant bits, and the output circuit (25) keeps the second pulse width modulated signal active for one additional clock cycle to fully convert to two's complement form, without the need for a carry operation.

Abstract: A communication system for coordinated downstream diversity transmission includes a central processing center for selecting adaptive transmitter parameters and adaptive receiver parameters to as to optimize an estimate of a transmitted data symbol received by a given mobile unit while constraining power output as well as accounting for interference to other mobile units within the propagation range of base units controlled by the central processing center. The adaptive transmitter and receiver parameters are determined from the solution of an eigenvalue formulation expressed in terms of the transmission path characteristics between the mobile unit and the base unit as well as transmission signal sources and mobile unit processing filters.

Abstract: An MSK receiver includes a downconverter for downconverting the received MSK signals. The phase drift or phase error per bit of the message preamble is determined. The reference carriers are generated, and the phase of the reference signals is adjusted during message demodulation under the control of the estimated rate of phase change across the preamble portion. In accordance with another aspect of the invention, the downconverted MSK signal burst is digitized and the digitized burst signal is stored in memory, following which it is read repeatedly so that bit timing, start-of-message timing, carrier phase, and carrier drift processing may be performed in a desired sequence, using all the available information for more accurate demodulation. According to a yet further aspect of the invention, a second order tracking loop is used to adjust the phase of the demodulation reference signals.

Abstract: An asynchronous data channel for a disk drive reads fields of data synchronized at a bit frequency which are separated by adjustment regions having two different patterns of control signals. Each pattern repeats at a different submultiple of the bit frequency. The channel derives two clock signals at the two submultiple frequencies, and produces a synchronizing signal related to the phase coincidence of the two clock signals. The synch signal indicates the start of the dam field. The channel can also produce the control-signal patterns and write them to a disk.

Abstract: Routing logic (RL) for a communication switching element (ISE) of a self-routing multi-stage switching network and able to transfer cells or packets of information from any of its inlets (I1/32) to any of its outlets (O1/32). The outlets of the switching element are arranged in routing groups containing one or more of them and of which the identity is derived by the routing logic from an output-port-address (OPA) identifying an output of the switching network and contained in the self-routing-tag (SRT) associated to the cell. This cell is then transferred to one of the outlets belonging to the selected routing group. The routing logic (RL) is also able to control the transfer of a cell through the switching element according to the execution of a predetermined routing function selected amongst a plurality of routing functions (RS, DI, MC, BH, IS).

Abstract: An FSK data receiving system is provided which is capable of constituting a direct-conversion receiver suitable for realizing an integrated circuit, is capable of decoding in a wide receiving band width, and is capable of realizing a small-sized and less-electric power consumption data receiving. An FSK-modulated local oscillator signal 3 is applied to a local oscillator 2, and there is provided a decode circuit 15 which obtains the decode signal 14 by judging whether the FSK-modulated frequency deviation of the carrier wave signal 1 is a positive deviation or a negative deviation on the basis of a comparison result of a voltage change in a frequency-voltage conversion circuit 16 for a base-band signal 8; i.e. the output signal of a frequency mixer 6.

Abstract: A self synchronizing automatic correlator, comprising apparatus for receiving an input data signal; apparatus for receiving a free running clock signal; a clock recovery circuit for comparing the input data signal and the free running clock signal and generating a phase error signal responsive thereto, and for frequency adjusting the clock signal by an amount equal to the phase error signal and in response generating a recovered clock signal synchronized to the input data signal; a shift register for receiving and storing the input data signal under control of the recovered clock signal; apparatus for storing a user data signal; and apparatus connected to the shift register and the apparatus for storing for comparing the input data signal and the user data signal and in the event of a match therebetween generating an output signal for indicating valid detection of the input data signal.

Abstract: A digital modulation technique is disclosed which is unique in that it does not utilize fixed time slots for varying the characteristics of an electromagnetic carrier signal, but actually uses variations of the time slots to transfer the digital information. The modulation is created by using direct digital synthesis techniques to produce a carrier waveform that closely approximates a sine wave carrier signal that can vary the time it takes for each peak to occur. The peaks of the carrier are tightly controlled to occur at exact discrete time slots that correspond to certain base band digital data. The time slot changes occur precisely at the sine wave peaks to minimize the bandwidth requirement and maximize the data rate.

Abstract: In a speech packet transmission system, a transmitter (speech terminal) first linearly predicts a speech signal input at a predetermined sample period from the input signal in the past and outputs the difference between the input speech signal and the prediction signal. A prediction coefficient used for linear prediction at this time is adapted with an output differential coded value at each predetermined sample period such that the prediction value is as close as possible to the value of the input waveform. The difference between the input speech signal and the prediction signal is converted to a differential code. A packet is prepared from a plurality of differential codes obtained during a frame period concerned and transmitted to a transmission line. A bit accuracy indicative of the differential code and a bit accuracy indicative of the differential coded value used for adaptation of the prediction coefficient are changed depending on the nature or property of the input speech signal.

Abstract: In a distortion compensating circuit, an initial value sufficient to provide a distortion compensating effect is previously set in a memory storage for storing distortion compensating data, whereby the convergence time of the distortion compensating effect is shortened.

Abstract: A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information.

Abstract: A transceiver (100) is provided for transmitting during the transmission bursts (12) of a frame and receiving during the receiving time-slot windows (14). The transceiver (100) includes a receiver (320) for receiving a repeating radio frequency data (16) signal at any time within the receiving time-slot window (14) and for demodulating the repeating radio frequency data signal down to a baseband data signal. A data detector and clock recovery device (330) recovers the valid data (CHMP) from the baseband data signal. For controlling the receiver (320) and data detector and clock recovery device (330), a control circuit (400) modifies the receiving time-slot windows (14) to only receive and detect when valid data is expected (52).

Abstract: A decision-directed phase-locked loop for not synchronizing with opposite phases where the proper data of a PRS channel reproduced signal do not exist. The loop comprises a digital loop filter, a ternary level predicting portion, a phase modification signal generating portion and an instantaneous phase detecting portion. The phase value of a future data existing point is first obtained on the basis of the phase value of the current data existing point in a reproduced signal output from the digital loop filter. The ternary level predicting portion predicts future data of the reproduced signal based on the phase value of the future data existing point and on future sampled values of the reproduced signal. Given the predicted future data, the phase modification signal generating portion checks to see if the current zero cross point of the reproduced signal is a data existing point.

Abstract: In a remote control signal repeater, which transmits remote control signals from a remote controller to a main device, having a bandpass filter and a level slicer, the bandpass filter is constructed of a parallel LC resonant circuit and a serial LC resonant circuit connected to each other. The resonant frequencies of the respective resonant circuits are set to the substantially same frequency. A resultant resonant characteristic having two peaks on sides of the original resonant frequency of the parallel LC resonant circuit is obtained and resonance of the serial LC resonant circuit is produced between the two peaks, thereby flattening the portion between the two peaks. The level slicer connected to the bandpass filter includes a class-C amplifier which level-slices output of the bandpass filter, a smoothing circuit which smoothes output of the class-C amplifier and a bias control circuit which variably controls the degree of class-C bias in accordance with a smoothed output of the smoothing circuit.

Abstract: Broadcasting system digitizes audio input signals before RF modulating and transmitting over airwaves to one or more remote receiving stations. Receiving station recovers the digitized signal by demodulating and exponentially expanding the received RF signal. Recovered digital signal is subsequently frequency modulated and sent, via an electrically conductive cable, to an FM radio, over which the original audio input signals are faithfully reproduced. A time switch in series with the RF receiver and the FM modulator is capable of temporarily disabling modulated transmissions to radio through the electrically conductive cable. Relay stations, (either land-based or satellite), allow for transmission beyond the range (i.e. "line-of-sight") of common FM radio transmissions.

Abstract: An electronic distribution system and method for combining a digital data signal, such as digital broadcast material, with instructions and a destination list for electronic delivery to a distribution center over a communications circuit connectable to a predetermined set of remote destinations. At the distribution center, the destination list is accessed and a copy of the digital data signal and the instructions are forwarded to only those remote destinations on the destination list.

Abstract: An implementation efficient digital timing recovery circuit capable of being implemented without the use of multipliers. The circuit includes a voltage controlled crystal oscillator ("VCXO"), a signal generator, a non-linear operation circuit, a digital bandpass filter, a bi-quadratic filter, a digital phase lock loop circuit (DPLL) and a zero crossing detector circuit. The circuit implements a spectral line extraction technique for symbol timing recovery. A signal is received by a tuner, passed through an analog to digital converter, whose sampling rate is controlled by the timing recovery circuit, and is then supplied to a Nyquist filter. The In-phase and quadrature-phase signals output by the Nyquist filter are passed through the non-linear operation circuit to produce a signal which is then passed through the bandpass filter and then the bi-quadratic filter which has a passband centered at the symbol rate of the received signal.

Abstract: Data communication equipment incorporating a matrix switch 11 and a control section 19 in which the matrix switch 11 is provided between M terminal interface units 12.sub.1 -12.sub.M and N communication channel interface units 13.sub.1 -13.sub.N and is capable of switching the combination of the N communication channels 10.sub.1 -10.sub.N and the M data terminal units 18.sub.1 -18.sub.M to enable mutual connections between a desired pair of communication channel and interface units. The controller 19 controls the matrix switch 11 and prescribes the appropriate connections between one of the N communication channel interface units 13.sub.1 -13.sub.N and one of the M terminal interface units 12.sub.1 -12.sub.M. Both the N communication channel interface units 13.sub.1 -13.sub.N and the M terminal interface units 12.sub.1 -12.sub.M are capable of inserting or extracting the connections to the matrix switch 11 on a unit-to-unit basis by means of a pair of N terminal groups 15.sub.1 -15.sub.

Abstract: A system and method for correcting for Rayleigh interference of a signal transmitted upon a multi-path channel. The system adaptively calculates values of channel gain and noise variance of the channel upon which the signal is transmitted, and generates signals indicative of such calculations which are supplied to a decoder. The system may be utilized to form a portion of a coherent, or noncoherent receiver which receives encoded and differentially-encoded signals.

Abstract: A DQPSK delay detection circuit includes a semi-synchronous detector synchronously detecting an input signal to obtain two demodulated signals, a low-pass filter for extracting a baseband signal from the demodulated signals, an A-D convertor sampling the baseband signal by a clock signal with a frequency 32 times higher than a symbol rate frequency and converting them to digital values with a predetermined number of quantization bits, a clock pulse generator generating clock signals synchronized with the baseband signal and having a frequency equal to and two times as high as the symbol rate frequency with a phase adjusted in accordance with a change of an eye pattern of an output of the A-D convertor, a data delay unit delaying the output of the A-D convertor by a time equivalent to one time slot according to a clock signal synchronized with the baseband signal and having a frequency equal to the symbol rate frequency, an operation unit generating signals I and Q from the output of the A-D convertor and a on